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CHAPTER 1 – INTRODUCTION
RST* is not a bidirectional, open-drain signal at the target connectors.
Removing the jumper leaves the RST-IN* signal pulled up to MCU operating
voltage.
1.3.2.5
Device Configuration Selection
The operation mode of the ABICS processor is selected at the rising edge of
the RESET signal. The ABICS requires that the processor operate in monitor
mode. To set monitor mode operation, the IRQ* line to the ABICS is level
shifted to apply V
signal name that is specified as minimum V
the highest V
maximum 9 V.
The ABICS RST* pin is the main mode select input and is pulled to logic 0,
then logic 1 (processor V
must communicate security bytes to the MCU to resume execution out of reset.
Communication to the monitor ROM is via standard, non-return-to-zero (NRZ)
mark/space data format on PTA0. The MCU maintains monitor mode and
disables the COP module through continued application of V
or RST*.
Six commands may be issued by the host software in control of the MCU in
monitor mode: read, write, iread, iwrite, readsp, and run. Each
command is echoed back through PTA0 for error checking. These commands
are described in the M68ICS08AB IN-CIRCUIT SIMULATOR SOFTWARE
OPERATOR'S MANUAL.
The MCU bus clock is CGMXCLK/2.
1.3.2.6
Level Translation
The ABICS has an operation voltage range of +3.0 to +5.0 volts while the host
development system interface is an RS-232 (com) port. U2 on the ICS converts
5 V logic signals to RS-232 levels. Transistors Q9-Q10 translate 5 V logic
levels to the MCU operating voltage (3.0-5.0 V).
1-8
to the processor on the rising edge of reset. The V
HI
of 3.3 V, which gives a range of minimum 5.8 V and
DD
), to select MCU monitor mode. The host software
DD
+ 2.5 V and maximum 9 V, with
DD
on either IRQ*
HI
M68ICS08ABUM/D
is a
HI
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