Acceptable I/O Bridge Settings; Bcm1125H Peripheral Devices; Table 8: Acceptable I/O Bridge Settings; Table 9: Smbus Peripherals - Broadcom BCM91125PCIX User Manual

User Manual
07/02/04
A I/O B
CCEPTABLE
The BCM1125H contains two bridges which isolate many of the chip's SOC components from the core, L2
cache, and other components. More details about these bridges can be found in the user manual for the
specific chip. The clocking for these bridges is determined by dividing the CPU clock. The allowable divide
ratios for a given bridge at a certain CPU frequency are provided below.
See Table 6 on page 16
CPU Clock (MHz)
600-650
700-1000
BCM1125H P
ERIPHERAL
SMBus Channel
0
0
0
0
1
Chip Select #
CS0
CS1
CS3
CS4
CS5
CS6
Document 91125PCIX-UM100-R
S
RIDGE ETTINGS
for the details on setting these values.

Table 8: Acceptable I/O Bridge Settings

IOB0 Divide Ratio
3 or 4
3 or 4
D
EVICES

Table 9: SMBus Peripherals

SMBus Address
0x2A
0x50
0x54
0x55
0x68

Table 10: Generic Bus Peripherals

Description
Hynix HY29LV160 boot flash memory or ROM Emulator (depending on J76 setting)
ROM Emulator or Hynix HY29LV160 boot flash memory (depending on J76 setting)
Infineon SLG2016 four character LED display
Cypress SL811HS USB Slot 0
Cypress SL811HS USB Slot 1
Compact Flash (CF) Slot
B roadc om C or por ati on
IOB1 Divide Ratio
2 or 3
3
Description
Maxim MAX6654 temperature sensor
Microchip 28LC128C EEPROM
DDR SDRAM DIMM Slot 0 SPD
DDR SDRAM DIMM Slot 1 SPD
ST Microelectronics M41T81 RTC

Acceptable I/O Bridge Settings

BCM91125PCIX
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