Output Differential Termination; Lvds, Cml - SiTime SiT6502EB User Manual

SiT6502EB Evaluation Board (EVB) HW User Manual
CLK1_DUT_P
DNP
RSE2
CLK1_DUT_P
453E
CSE2
10pF
DNP
CSE6
10pF
DNP
DNP
RSE6
CLK1_DUT_N
453E
CLK1_DUT_N

11.1 Output Differential Termination

LVDS (default configuration), LVPECL, HCSL, and CML differential signaling types can be supported by
changing the output termination circuits.

11.1.1 LVDS, CML

The board is shipped to support LVDS, CML in its default differential. The signals are ac coupled with
ceramic 0.1 uF capacitors instead of the corresponding series resistors RSExx (Refer to
are not populated.
Table 6. Output Port RSExx Resistors
Output Port # 0
RSE1
0.1 uF capacitors
RSE5
Output termination resistors as shown in
SiT6502EB HW UM Preliminary Rev 1.0
CLK1_OUT_P
R114
49.9
DNP
R118
49.9
CLK1_OUT_N
DNP
Figure 7. Output Clock Termination Circuit
1 2 3
RSE2 RSE4 RSE3
RSE6 RSE7 RSE8
Table 7 are not populated.
Page 10 of 33
J44
R111
1
CLK1_OUT_P
0
GND
JSCL14
2
VCM_1
JSCL2
C70
C71
1 uF
10 uF
GND
J49
R123
1
CLK1_OUT_N
0
GND
4 5 6
RSE10 RSE9 RSE11
RSE14 RSE13 RSE15
CONNECTOR COAX-P_3PIN
1
GND
CONNECTOR COAX-P_3PIN
Table 6) which
7 0B 0T
RSE12 RSE17 RSE18
RSE16 RSE19 RSE20
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