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SiT6722EB Evaluation Board User Manual
SiT6722EB Evaluation Board User Manual
Contents
1 Introduction ............................................................................................................................................. 1
2 I/O Descriptions ....................................................................................................................................... 2
3 EVB Usage Descriptions ........................................................................................................................... 2
3.1 EVB Configurations........................................................................................................................ 2
2
C Support ....................................................................................................................... 3
3.2 Waveform Capturing Using Active Probe ..................................................................................... 3
3.3 Measuring Jitter and Phase Noise ................................................................................................. 4
3.4 Current Measurement .................................................................................................................. 4
Appendix A .................................................................................................................................................... 5
1
Introduction
The SiT6722EB evaluation board (EVB) is designed for use with SiTime's Elite Super-TCXOs in the 10-pin,
5.0x3.2 mm ceramic packages. It enables the evaluation of key functionalities of these precision Super-
TCXOs in three configuration modes: TCXO, VCTCXO and DCTCXO with I
EVB Features
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Support for three Super-TCXO configuration modes: TCXO, VCTCXO, DCTCXO
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Direct SMA outputs for frequency/jitter measurements
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Probing points for waveform measurements
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Connector access for controlling the output frequency via I
SiTime typically ships the EVB with the Super-TCXO mounted using SiTime recommended reflow profile.
The Super-TCXO device should only be evaluated in its original soldered down state for best signal
integrity and frequency stability. The device performance is not guaranteed if it is de-soldered and then
re-soldered either manually or via reflow process.
SiT6722EB UM Rev 3.0
2
C
Page 1 of 8
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C.
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Summary of Contents for SiTime SiT6722EB
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Page 1: Table Of Contents
Appendix A ..............................5 Introduction The SiT6722EB evaluation board (EVB) is designed for use with SiTime’s Elite Super-TCXOs in the 10-pin, 5.0x3.2 mm ceramic packages. It enables the evaluation of key functionalities of these precision Super- TCXOs in three configuration modes: TCXO, VCTCXO and DCTCXO with I... -
Page 2: O Descriptions
EVB Usage Descriptions EVB Configurations SiT6722EB can be configured to support three Super-TCXO configuration modes including TCXO with output enable (OE), VCTCXO with analog voltage control and DCTCXO with I Oscillator output waveform can be measured with an active probe in all configurations. The value of the load capacitor C5 can be adjusted to match the load conditions in the target application. -
Page 3: I 2 C Support
C master does not have it). If requested, the EVB will ship with these resistors. Waveform Capturing Using Active Probe SiTime Elite Super-TCXO is a high-speed logic output device. It is critical that the proper logic and high frequency measurement techniques are used along with the high-quality active probe to ensure best measurement results. -
Page 4: Measuring Jitter And Phase Noise
Eliminating such distortion requires a probe with the lowest input capacitance and a low inductance ground lead. In addition, SiTime Super-TCXOs are typically configured for fast rise and fall times (1 ns or less) with 15 pF load. It is therefore critical that the probe tip ground be as short as possible, lowest inductance, and the return path for the ground be located as close as possible to the trace carrying the RF logic signal. - Page 5 Place close to DUT pin1 Pad8 Pad9 Pad7 Pad10 Pin1 OE/VC/NC SDA/NC SCL/NC CON/HDR 5pinX1row A0/NC "out" SiTime_10pin_SE_Ceramic SMA edge mount 0402 0603 Pad2 Vdd_sense 0.10uF 0603 NPO0603 0603 Figure A1. SiT6722EB EVB Electrical schematics Page 5 of 8 www.sitime.com...
- Page 6 SiT6722EB Evaluation Board User Manual Table A1. Bill of Materials (BOM) Reference Designators Description SMD component size Value C1, C3 Capacitors 0603 10uF Capacitor 0402 0.1uF Capacitor 0402 Capacitor 0603 Capacitor 0603 0.1uF C7, C8 Capacitor 0402 0603 Green Resistors 0603 50 Ω...
- Page 7 SiT6722EB Evaluation Board User Manual Probe test points Signal Figure A2. SiT6722EB EVB SiT6722EB UM Rev 3.0 Page 7 of 8 www.sitime.com...
- Page 8 © SiTime Corporation, May 2022. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liabi lity for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.
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