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SiT6732EBB Evaluation Board User Manual
Contents
1 Introduction ............................................................................................................................................. 1
2 I/O Descriptions ....................................................................................................................................... 2
3 EVB Usage Descriptions ........................................................................................................................... 3
3.1 EVB Configurations........................................................................................................................ 3
3.2 Waveform Capturing Using Active Probe ..................................................................................... 4
3.3 Measuring Jitter and Phase Noise ................................................................................................. 4
3.4 Current Measurement .................................................................................................................. 5
Appendix A .................................................................................................................................................... 6
1

Introduction

The SiT6732EBB evaluation board (EVB) is designed for use with SiTime's Epoch OCXOs in the 10-pin 9x7
mm package and LVCMOS output type. It enables the evaluation of key functionalities of these OCXOs.
The analog buffer isolates the device from the significant loading, which is important for performing
best phase noise measurements.
EVB features
-
SMA output for direct or buffered connection to measurement equipment
-
Probing points for accurate waveform measurement
2
-
Provision for I
C/SPI control interface
SiTime typically ships the EVB with the OCXO mounted. The OCXO device should only be evaluated in its
original soldered down state for best signal integrity and frequency stability. For best results the device
should not be de-soldered and then re-soldered either manually or via reflow process.
The SiT6732EBB supports the following products:
Base Part Number
SiT5801
SiT5802
SiT5811
SiT5812
SiT7101
SiT7102
SiT7111
SiT7112
SiT6732EBB User Manual | Rev 2.2
Type
OCXO
OCXO
OCXO
OCXO
DCOCXO
DCOCXO
DCOCXO
DCOCXO
Page 1 of 10
Output frequency
1 MHz to 60 MHz
60 MHz to 220 MHz
1 MHz to 60 MHz
60 MHz to 220 MHz
1 MHz to 60 MHz
60 MHz to 220 MHz
1 MHz to 60 MHz
60 MHz to 220 MHz
Package
9.0 x 7.0 SMT
9.0 x 7.0 SMT
9.0 x 7.0 SMT
9.0 x 7.0 SMT
9.0 x 7.0 SMT
9.0 x 7.0 SMT
9.0 x 7.0 SMT
9.0 x 7.0 SMT
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Summary of Contents for SiTime SiT6732EBB

  • Page 1: Table Of Contents

    Appendix A ..............................6 Introduction The SiT6732EBB evaluation board (EVB) is designed for use with SiTime’s Epoch OCXOs in the 10-pin 9x7 mm package and LVCMOS output type. It enables the evaluation of key functionalities of these OCXOs. The analog buffer isolates the device from the significant loading, which is important for performing best phase noise measurements.
  • Page 2: O Descriptions

    Buffered output through SMA connector Oscilloscope probe at probing points Direct output through SMA connector Direct output through LVCMOS-to-sinewave filter and SMA connector Please refer to the Section 3.1 for the details. SiT6732EBB User Manual | Rev 2.2 Page 2 of 10 www.sitime.com...
  • Page 3: Evb Usage Descriptions

    SiT6732EBB. Components labeled “DNP” are not assembled. Power supply configuration SiT6732EBB support separate supply for the OCXO and on-board buffer. The VDD of the buffer should be equal to the VDD of the OCXO. C configuration The two pull-up resistors R14 and R15 with 4.7 kΩ...
  • Page 4: Waveform Capturing Using Active Probe

    For waveform measurement, it's recommended to remove resistor R5 and R4. Please refer to Figure A2 for test point locations on the SiT6732EBB. If soldering probe head is used, it is recommended to use R5 resistor pad for CLK signal and C12 capacitor pad for GND (Figure 1).
  • Page 5: Current Measurement

    It is recommended to measure the voltage on DUT VDD and adjust for any drop on the DMM to ensure known VDD voltage on the device. VDD adjustment must be completed before every current measurement. SiT6732EBB User Manual | Rev 2.2 Page 5 of 10 www.sitime.com...
  • Page 6 SDA/MISO TEST_7 NF/MISO/SDA Buff_Out Buff_Out CLK_IN Buf_VCC SiTime_10pin MOSI Pad9 LMK1C1102 Pad10 Pad11 0.1uF 10uF Pad12 VDD_filt VDD_filt Pad13 OE/NC MOSI Pad14 SDA/MISO Pad15 Figure A1: SiT6732EBB electrical schematics SiT6732EBB User Manual | Rev 2.2 Page 6 of 10 www.sitime.com...
  • Page 7 0402 R13, R19, R20 R5, R6, R11, R12 Resistors 0402 0 Ω R14, R15, R16, R18 Resistors 0603 Resistor 0603 0 Ω Resistor 0402 0.68 Ω Buffer TSSOP8-TI LMK1C1102 SiT6732EBB User Manual | Rev 2.2 Page 7 of 10 www.sitime.com...
  • Page 8 Device Power/Power adjust WM10299-ND WM2002-ND WM1114TR-ND Pin 1 access WM10297-ND WM2011-ND Buffer Power WM10297-ND WM2011-ND Frequency control via I C/SPI WM10300-ND WM2014-ND 343- CONSMA020.062-G- SiT6732EBB User Manual | Rev 2.2 Page 8 of 10 www.sitime.com...
  • Page 9 SiT6732EBB Evaluation Board User Manual Probe test points VDD sense Signal Figure A2: SiT6732EBB layout SiT6732EBB User Manual | Rev 2.2 Page 9 of 10 www.sitime.com...
  • Page 10 © SiTime Corporation, February 2025. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.