Advertisement
Quick Links
SiT6097EB Evaluation Board User Manual
SiT6097EB Evaluation Board User Manual
Contents
1 Introduction ............................................................................................................................................. 2
2 I/O Descriptions ....................................................................................................................................... 3
3 EVB Usage Descriptions ........................................................................................................................... 3
3.1 EVB Configurations........................................................................................................................ 3
3.1.1 LVPECL, Standard Termination, Active Probe .................................................................. 4
3.1.2 LVPECL, AC-coupling Configuration, Direct to Instrument ............................................... 4
3.1.3 LVPECL, Y-Termination, Active Probe ............................................................................... 5
3.1.4 LVPECL, Split Ground, Direct to Instrument ..................................................................... 6
3.1.5 LVDS, Standard Termination, Active Probe ...................................................................... 6
3.1.6 LVDS, AC-coupling Configuration, Direct to Instrument .................................................. 7
3.1.7 HCSL, Standard Termination, Active Probe ...................................................................... 7
3.1.8 HCSL, Standard Termination, Direct to Instrument ......................................................... 8
3.2 Waveform Capturing Using Active Probe ..................................................................................... 8
3.3 Measuring Jitter and Phase Noise ................................................................................................. 9
3.4 Current Measurement .................................................................................................................. 9
Appendix A .................................................................................................................................................. 10
SiT6723EBB manual Rev 1.0
Page 1 of 13
www.sitime.com
Advertisement
Related Manuals for SiTime SiT6097EB
Summary of Contents for SiTime SiT6097EB
- Page 1 SiT6097EB Evaluation Board User Manual SiT6097EB Evaluation Board User Manual Contents 1 Introduction ............................. 2 2 I/O Descriptions ............................3 3 EVB Usage Descriptions ........................... 3 3.1 EVB Configurations........................3 3.1.1 LVPECL, Standard Termination, Active Probe ..............4 3.1.2 LVPECL, AC-coupling Configuration, Direct to Instrument ..........4 3.1.3 LVPECL, Y-Termination, Active Probe ................
- Page 2 SiT6097EB Evaluation Board User Manual Introduction The SiT6097EB evaluation board (EVB) is designed for use with SiTime’s XO in the 6-pin, 3.2 x 2.5 mm packages and LVPECL, LVDS or HCSL output type. The SiT6097EB supports the following products: Base Part Number...
- Page 3 EVB Usage Descriptions EVB Configurations SiT6097EB can be configured to support three configuration modes including XO/TCXO with output enable (OE), XO in Standby (ST), Spread Disabled (SD), Voltage Control (VC) or Digital Control (DC). The test points for active probe are placed closely to the oscillator output for better signal integrity (see Figure A2 and sections 3.1.1, 3.1.3, 3.1.5, 3.1.7).
- Page 4 SiT6097EB Evaluation Board User Manual Components labeled “DNP” are not assembled. Any components which nominal are not shown on the schematic will be not populated by default unless it is defined by the specific configuration. 3.1.1 LVPECL, Standard Termination, Active Probe In this configuration, the LVPECL outputs are terminated to Vbias = VDD –...
- Page 5 SiT6097EB Evaluation Board User Manual OUT_- "out-" 0.1uF Pin1 Pin1 Pin2 OUT_n R12 = R25 = 100 Ohm for 3.3V VDD Pin2 OUT- R12 = R25 = 48.7 Ohm for 2.4V VDD Vbias OUT+ OUT_p SiTime_6pin OUT_+ "out+" 0.1uF DUT_GND Figure 2.
- Page 6 SiT6097EB Evaluation Board User Manual 3.1.4 LVPECL, Split Ground, Direct to Instrument By splitting the power supply with VDD set to 2 V referenced to ground and Vbias set to -1.3 V (for 3.3 V across DUT) or -0.5 V (for 2.5 V across DUT) referenced to ground, the OUT+ and OUT- are effectively biased at ground potential.
- Page 7 SiT6097EB Evaluation Board User Manual 3.1.6 LVDS, AC-coupling Configuration, Direct to Instrument This is default shipment configuration for evaluation boards with LVDS devices. This configuration is useful for connecting LVDS outputs to 50 Ω input channels of the measurement instrument. The AC-coupling capacitors (R16 and R23) block the DC common mode voltage from the LVDS outputs to avoid DC current draw to the 50 Ω...
- Page 8 10 Ω to 30 Ω series resistors at source side. Waveform Capturing Using Active Probe SiTime XO/TCXO is a high-speed logic output device. It is critical that the proper logic and high frequency measurement techniques are used along with the high-quality active probe to ensure best measurement results.
- Page 9 SiT6097EB Evaluation Board User Manual Figure 9. Differential browser (high impedance active probe) on test points for waveform capture on SiT6097EB. More details on the SiTime recommendations on the oscillator’s output probing can be found in AN10028. Measuring Jitter and Phase Noise...
- Page 10 SiT6097EB Evaluation Board User Manual Appendix A Place away from P1 and P4 10uH Vdd_sense CON/HDR 3pinX1row 10uF 0.1uF Pin1 Pin2 Place close to DUT VDD pin "curr_meas_inp" CON/HDR 3pinX1row CON/HDR 3pinX1row 10uF "curr_meas_out" CON 2pinX1row DUT_GND DUT_GND DUT_GND Vbias...
- Page 11 SiT6097EB Evaluation Board User Manual Table A1: Bill of Materials (BOM) Reference Description Value Designators component size R1, R14, R19, R28 Resistor 0603 0 Ω R2, R9, Resistor 0603 10 Ω R5, R6 Resistor 0603 51 Ω R29, R31 Resistor 0603 51 kΩ...
- Page 12 SiT6097EB Evaluation Board User Manual Out- VDD sense Probe test points Out+ Figure A2: SiT6097EB layout SiT6723EBB manual Rev 1.0 Page 12 of 13 www.sitime.com...
- Page 13 © SiTime Corporation, December 2023. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.
Need help?
Do you have a question about the SiT6097EB and is the answer not in the manual?
Questions and answers