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Contents
1 Introduction ............................................................................................................................................. 1
2 I/O Descriptions ....................................................................................................................................... 2
3 EVB Usage Descriptions ........................................................................................................................... 3
3.1 EVB Configurations........................................................................................................................ 3
2
3.1.1 I
C Support ....................................................................................................................... 3
3.2 Waveform Capturing Using Active Probe ..................................................................................... 4
3.3 Measuring Jitter and Phase Noise ................................................................................................. 5
3.4 Current Measurement .................................................................................................................. 6
Appendix A .................................................................................................................................................... 7
1
Introduction
The SiT6723EBBC evaluation board (EVB) is designed for use with SiTime's Elite
10-pin, 7.0 x 5.0 mm x mm ceramic packages and Clipped Sinewave output type. It enables the
evaluation of key functionalities of these precision Super-TCXOs in two configuration modes: TCXO and
2
DCTCXO with I
C.
The SiT6723EBBC supports 7.0 x 5.0 mm x mm package size including the following products:
Base Part Number
SiT5501
SiT5503
SiT5541
SiT5543
SiT6723EBBC User Manual | Rev 1.1
Type
Super-TCXO
Super-TCXO
Ruggedized Super-TCXO
Ruggedized Super-TCXO
Page 1 of 11
X™
Output frequency
1 MHz - 60 MHz
1 MHz - 60 MHz
1 MHz - 60 MHz
1 MHz - 60 MHz
Super-TCXOs in the
Package
7.0 x 5.0 CQFN
7.0 x 5.0 CQFN
7.0 x 5.0 CQFN
7.0 x 5.0 CQFN
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Summary of Contents for SiTime SiT6723EBBC
-
Page 1: Table Of Contents
10-pin, 7.0 x 5.0 mm x mm ceramic packages and Clipped Sinewave output type. It enables the evaluation of key functionalities of these precision Super-TCXOs in two configuration modes: TCXO and DCTCXO with I The SiT6723EBBC supports 7.0 x 5.0 mm x mm package size including the following products: Base Part Number Type... -
Page 2: Sit6723Ebbc Evaluation Board User Manual
Probing points for accurate waveform measurement Connector access for controlling the output frequency via I2C SiTime typically ships the EVB with the Super-TCXO mounted using SiTime recommended reflow profile. The Super-TCXO device should only be evaluated in its original soldered down state for best signal integrity and frequency stability. -
Page 3: Evb Usage Descriptions
“DNP” are not assembled. Shipment Configuration SiT6723EBBC is shipped configured for buffered output allowing connecting it to the instrument input using 50 Ω coax cable. Details on the board assembly for shipment configuration can be found on the schematic (see... -
Page 4: Waveform Capturing Using Active Probe
For waveform measurement, it's recommended to remove resistor R26. Please refer to Figure A2 test point locations on the SiT6723EBBC. If the soldering probe is used, it is recommended to use R28 resistor pads or solder it over it if necessary (Figure 1). -
Page 5: Measuring Jitter And Phase Noise
Figure 2: Signal measurement using probe Measuring Jitter and Phase Noise For jitter and phase noise measurements, buffered output configuration is recommended. SiTime TCXO was not designed to drive 50 Ω load directly so buffer avoids excessive current draw from the device output. -
Page 6: Current Measurement
It is recommended to measure the voltage on DUT VDD and adjust for any drop on the DMM to ensure known VDD voltage on the device. VDD adjustment must be completed before every current measurement. SiT6723EBBC User Manual | Rev 1.1 Page 6 of 11 www.sitime.com... - Page 7 Pin1 Pin2 Test CLK_IN Buff_VCC Buff_Out 0.1uF LMK1C1102PWR 0.1uF Buff_Out Output Pad5 DUT_Vdd Vdd_sense 0.1uF Pad6 Pad7 Pad8 Pad9 Pad10 Pad11 Pad12 Pad13 Pad14 Figure A1: SiT6723EBBC electrical schematics SiT6723EBBC User Manual | Rev 1.1 Page 7 of 11 www.sitime.com...
- Page 8 0402 20 kΩ R23, R24, R25, R28 Resistors 0402 Resistor 0603 51 kΩ Buffer TSSOP8-TI LMK1C1102 4-pin header P2, P3, P4, P5, P6 2-pin headers 5-pin header SMA connector SiT6723EBBC User Manual | Rev 1.1 Page 8 of 11 www.sitime.com...
- Page 9 Connectors part number mating connector associated products Power/Power adjust WM10299-ND WM2002-ND WM1114TR-ND Buffer power WM10297-ND WM2011-ND Buffer power supply jumper Z5275-ND S9342-ND Frequency control via I2C 2057-PH1RB-05-UA-ND SiT6723EBBC User Manual | Rev 1.1 Page 9 of 11 www.sitime.com...
- Page 10 SiT6723EBBC Evaluation Board User Manual Probe test points VDD sense Signal Figure A2: SiT6723EBBC layout SiT6723EBBC User Manual | Rev 1.1 Page 10 of 11 www.sitime.com...
- Page 11 © SiTime Corporation, January 2025. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liabi lity for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.
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