CP6004-SA/-RA/-RC/CP6004X-SA
10.
XMC Card Support
The presence or absence of an XMC card is reported by the "XMC present" sensor (refer to
Chapter 7.1, Sensor List).
If an XMC card is present, the card's FRU data EEPROM is readable/writable. The size of the
EEPROM must be smaller or equal to 256 bytes because of 8-bit EEPROM addressing. Please
note that the XMC FRU size is always reported as 256 bytes and writing to locations that are
higher than the real capacity should be avoided.
The FRU data of the XMC card can be read under Linux using ipmitool fru print 1.
11.
uEFI BIOS Failover Control - Automatic SPI
Boot Flash Selection
The uEFI BIOS code is stored in two different SPI boot flash devices designated as the stan-
dard SPI boot flash and the recovery SPI boot flash.
By default, the uEFI BIOS code stored in the standard SPI boot flash is executed first. If this
fails, the uEFI BIOS code in the recovery SPI boot flash is then executed.
During boot-up, the uEFI BIOS reports its operational status to the IPMI controller within a given
time. If the status is "failed" or not reported within the given time, the IPMI controller selects the
recovery SPI boot flash, resets the board's processor, and waits for the status report from the
uEFI BIOS again.
In the event the recovery boot operation fails, the IPMI controller reports it, but takes no further
action of its own.
When a boot operation fails, a "Boot Error - Invalid boot sector" event is asserted for the related
sensor:
• "FWH0 Boot Err" sensor indicates the standard SPI boot flash has failed
• "FWH1 Boot Err" sensor indicates the recovery SPI boot flash has failed
For further information regarding the SPI boot flash selection, refer to Chapter 6.3, Set Control
State,Table 7.
12.
OS Boot Order Selection by OEM IPMI
Normally the uEFI BIOS will apply the OS boot order which was selected in the uEFI BIOS
menu "uEFI Boot/Boot Option Priorities". But there is another alternative boot order which is
stored in the IPMI controller's non-volatile memory. This boot order can be set and read by IPMI
OEM commands. At payload start the IPMI controller writes this boot order into a register where
the uEFI BIOS can read it. If this IPMI controller's boot order has a non-zero value, the uEFI
BIOS will use it instead of its own boot order.
For information regarding the boot order configuration, refer to Chapter 6.3, Set Control
State,Table 7.
ID 1053-0139, Rev. 3.0
IPMI Firmware
Page 37
Need help?
Do you have a question about the CP6004-SA and is the answer not in the manual?