I/O Address Map; Table 23: Designated I/O Port Address Ranges - Kontron COMe-cDV7 User Manual

Address Range (hex)
FEB0-0000 FEBF-FFFF
FEC0-0000 FEC0-0040
FED0-0000 FED0-03FF
FED4-0000 FED4-0FFF
FED6-0000 FED6-0FFF
FEE0-0000 FEEF-FFFF
FF00-0000 FF0F-FFFF
FF10-0000 FF1F-FFFF
FF20-0000 FF2F-FFFF
FF30-0000 FF3F-FFFF
FF40-0000 FF4F-FFF
FF50-0000 FF5F-FFF
FF60-0000 FF6F-FFF
FF70-0000 FF7F-FFF
FF80-0000 FF87-FFFF
FF88-0000 FF8F-FFFF
FF90-0000 FF97-FFFF
FF98-0000 FF9F-FFFF
FFA0-0000 FFA7-FFFF
FFA8-0000 FFAF-FFFF
FFB0-0000 FFB7-FFFF
FFB8-0000 FFBF-FFFF
FFC0-0000 FFF7-FFFF
FFF8-0000 FFFB-FFFF
FFF0-0000 FFFF-FFFF
4Gb to TOUUD – High DRAM Window
1_000-000 TOUUD-1
TOUUD to 1024 GB – High MMIO
TOUUD 1024 GB
[1]
legacy support is not validated by Intel

10.3. I/O Address Map

The I/O port addresses are functionally identical to a standard PC/AT. All addresses not mentioned in the following
table should be available. We recommend that you do not use I/O addresses below 0100h with additional hardware for
compatibility reasons, even if the I/O address is available.

Table 23: Designated I/O Port Address Ranges

I/O Address Range
(hex)
020-021
024-025
028-029
02C-02D
02E-02F
030-031
034-035
038-039
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Size Project Usage
Abort
I/O(X)APIC
High performance event timer
TPM- TPM1.2 range
XHCI DbC - no other MMIO must overlap this address range
Local APIC
BIOS4 Feature space for LPC
BIOS4 data space for SPI and LPC
BIOS3 feature space for LPC
BIOS3 data space for SPI and LPC
BIOS2 data space for SPI and LPC
BIOS – data space for SPI and LPC
High main memory. Top of Upper Usable DRAM
High MMIO (64-bit MMIO)
General Usage
Interrupt Controller (8259 PIC)
LPC
Interrupt Controller (8259 PIC)
Interrupt Controller (8259 PIC)
COMe-cDV7 - User Guide, Rev 1.0
Project Usage
Interrupt Controller
LPC
Interrupt Controller
Interrupt Controller
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