General Operation
The control bit (bit 2 in byte 0 of the status word) is set
•
after POWER ON while the IP 265 is being loaded from the memory submodule,
•
during loading of the IP 265 via the remote I/O bus and
•
shortly after selection of the COM 265 function "on-line test".
Status and error indication
In the case of an error, the IP 265 goes into STOP (exception: short-circuit at 24 V output). In
addition to the display of the operating state, the IP 265 provides error messages and further status
information.
Further status and error indications in the status word:
Byte 0
Byte 1
Figure 4-8. Error Messages and Status Information in the Status Word
Group error:
Instruction error:
4-10
7
6
5
4
3
The group error bit is set for every error.
If the instruction error bit is set, the instruction in the control word of the
preceding data cycle has not been processed. It shows the following:
•
A useless instruction; e.g. RUN and STOP bits are set concurrently in
the control word (signal state "1")
•
Incorrect parameter values (time values, counts outside the per-
missible range of values: 0 to 999)
1: Group error
2
1
0
0/1: Code for memory
1:
1:
1:
1:
1:
IP 265
submodule evaluation
( Table 4-3)
IP 265 is loaded
Module is faulty
(FPGA is defective)
I/O not ready
(wirebreak, short-circuit,
no 24 V DC supply)
Loading error
Instruction error
EWA 4NEB 812 6130-02a