Siemens SIMATIC S5 Manual page 201

IP 265 Expansion
Dynamic response
Over the expansion interface, a signal is delayed by 7.8 µs.
•
• The CPU user program uses the external I/O bus for error control and recovery and for
STOP/RUN control of both IP 265s. Since control word and status word for both IP 265s are
forwarded cyclically in one CPU data cycle, there is no delay when e.g. both IPs are to be set to
STOP.
Note
The expansion interface has no STOP or error signal line of its own.
• Parameter initialization for both IP 265s is also synchronous. Because input parameters and
output parameters are forwarded cyclically in one CPU data cycle, there is no delay in initializing
the two IPs.
CPU
PIQ
PII
Figure 12-1. Data Transfer Between CPU and Two Expanded IP 265s
12-2
External
I/O bus
Cyclic data transfer
(data cycle):
- Control word
- Status word
- Parameters
Expansion
IP 265 IP 265
FPGA FPGA
Expansion cable
Permanent data transfer
(delay=1 FPGA cycle: 7.8 µs):
- DI/DQ binary signals
IP 265
EWA 4NEB 812 6130-02a