Dut Routed To External Ate System - Pin Routing - Equinox Systems ISPnano IV-ATE Series Hardware User Manual

4.5 DUT routed to External ATE System – Pin routing
By default the RELAYs are OFF and the 'ATE Port' signals are routed to the 'Target ISP Port' pins
as detailed in the table below.
Target ISP ATE Port
Port Pin
Pin Number Number
1 + 2 1 + 2
3 + 4 3+4
5 + 6 5 + 6
7a 7a
7b 7b
7c 7c
8a 8a
8b 8b
8c 8c
9 N/C
10 N/C
11 11
12 12
13 13
14 14
15 15
16 16
16
Programmer
Pin name
TARGET_VCC
EXT_VCC
PROG_GND
•
I2C SCL
•
PDI_CLK
•
TPI_CLK
•
I2C_SDA
•
XMEGA_PDI_DAT
A
•
ATTINY_TPI_DATA
OP6
Programmer I/O5
Programmer I/O4
Programmer I/O3
Programmer I/O2
Programmer I/O1
PROG_VPP
PROG_RESET
ISPnano Series IV-ATE Programmer - User Manual – V1.04 – 21/02/2014
Notes
Target VCC
This pin should be connected to the
Target System Vcc.
Target External VCC
No connection required as EXT-VCC is
being used to control the RELAY coils.
Signal Ground Connection (1)
0V to which the programmer JTAG, SPI,
I2C, PDI, TPI signal lines are referenced
to.
•
I2C SCL clock signal
•
XMEGA PDI CLOCK Signal
•
ATtiny TPI CLOCK Signal
•
I2C SDA data signal
•
XMEGA PDI DATA Signal
•
ATtiny TPI DATA Signal
Spare Output (used for PDI / TPI)
Spare I/O pin
This pin is used for JTAG Target Systems
only.
This pin can be used for JTAG or SPI
Target Systems.
This pin can be used for JTAG, SPI,
UART, XMEGA PDI and ATtiny TPI
Target Systems.
This pin can be used for JTAG, SPI or
UART Target Systems.
Vpp Voltage
Target RESET control pin