Casio QG-100 Operation, Service Manual & Parts List page 12

GATE ARRAY (MN7A076KYL): LSI2 (Internal analog circuit of LSI2 is not used)
Pin No. Name
1 VSS
2~15 A10~A23
16 CS2
17 CE3R
18 CE3G
20 RFSH
21 PSOE
22~29 DR0~DR7
30~31,
DG0~DG7
34~39
32 VSS
33 VDD
48 SO1
49 PCLK1
50 SO2
51 PCLK2
52 LTCH
53 PSTB1
54 PSTB2
58 VDD
59 VSS
60~72 Analog terminal
73 VDD
74 VSS
75 Analog terminal
76 PON
77 POFF
78~80 Analog terminal
85 TCON
86 RSO
87 RSI
88 VDE
94~95 INT1~0
96 VSS
97 VDD
98 BUSGT
99 BUSRQ
100 RESET
101~108 CD7~CD0
109 CWR
110 CRD
111 SYSCLK
112 VSS
113 XIN
114 XOUT
115 VDD
116 CRFSH
117 CLK
118~127 A0~A9
128 VDD
I / O
— Digital ground for LSI2
I/O Address bus
O Chip select to static RAM(LSI4)
O Chip enable to PS-RAM(LSI5)
O Chip enable to PS-RAM(LSI6)
O Refresh signal to PS-RAM(LSI5,6)
O Output enable to PS-RAM(LSI5,6)
I/O Data bus for PS-RAM(LSI5)/color data(red & green)
I/O Data bus for PS-RAM(LSI6)/color data(blue) & work data
— Digital ground for LSI2
I Power supply for LSI2
O Serial data for thermal head(upper part of picture)
O Clock for thermal head(upper picture)
O Serial data for thermal head(lower part of picture)
O Clock for thermal head(lower picture)
O Latch pulse for data to thermal head
O Strobe signal for upper picture data to thermal head
O Strobe signal for lower picture data to thermal head
I Power supply for LSI2
— Digital ground for LSI2
— (not used)
I Power supply for LSI2
— Digital ground for LSI2
— (not used)
I Forced power on
I Forced power off
I (not used)
O Control for power(VP)(power on/off)
O Reset output from LSI2
I Reset signal to LSI2
I Detection of low voltage(VDD1=4.30~4.35 V)
O Interrupt signal for LSI1(CPU)
— Digital ground for LSI2
I Power supply for LSI2
I Bus grant signal from CPU(LSI1)
O Bus request to LSI1(CPU)
O Reset signal to LSI1(CPU)
I/O Data bus
I Write signal from LSI1(CPU)
I Read signal from LSI1(CPU)
I System clock from LSI1(CPU), 6 MHz
— Digital ground for LSI2
I Master clock for LSI2(input), 24 MHz
O Master clock for LSI2(output), 24 MHz
I Power supply for LSI2
I Refresh signal from LSI1(CPU)
O Clock for LSI1(CPU)
I/O Address bus
I Power supply for LSI2
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Function