Spectrum Digital TMS320DM6467 Technical Reference page 21

2.6.1 Audio PLL/VCXO Circuit/CDCE949 Clock Generator
The TMS320DM6467 EVM implements a multiple PLL clock generator via the
CDCE949 for creating the audio and optional video clocks for the board.
In streaming video applications the audio and video sequences can lose
synchronization. The TMS320DM6467 uses a VCXO interpolation circuit to
incrementally speed up or slow down the clocks to allow for this synchronization
to remain locked.
The PWM0 and timer input TIN0 or CRG0 and CRG0_VCXI are used to control this
feature on the EVM. The PWM0 or CRG0 pin drives VCTR on the CDCE949 which is
fed back into the timer input pin or the CRG0_VCXI pin on the DM6467.
This device creates the clocks for the AIC32 Codec, daughter card, and optional video
clocks. The CDCE949 is programmable via an I
by use of its fractional PLL architecture.
PWM0/CRGO
TMS320DM6467
TIN0 CRG0_VCXI
Figure 2-4, TMS320DM6467 Clock Circuitry
Spectrum Digital, Inc
2
C and support virtually any clock rate
Y1
VCTR
Y2
Y3
Y4
CDCE949
Y5
Y6
Y7
Y8
Y9
Audio Clock
2-7