Spectrum Digital TMS320DM6467 Technical Reference page 17

2.2.3 UART Interface
The internal UART0 on the TMS320DM6467 device is driven to connector P1. The
UART's interface is routed through CBT's to a Texas Instruments MAX3243 RS-232
line driver prior to being brought out to a male DB-9 connector, P8. The on board UART
signals can be disabled by pulling the UART0_EN signal high via the daughter card
connectors.
2.2.4 ATA Interface
The TMS320DM6467 EVM integrates a standard ATA interface on chip. This interface
is multiplexed with the PCI and I/O daughter card interfaces. When PCI or daughter
card interfaces are enabled the ATA interface is not available for development. The
EVM can directly interface to a standard lap top hard disk drive via connector JP2.
Power to the drive is controlled via I
2.3 DDR2 Memory Interface
The TMS320DM6467 device incorporates a dedicated 32 bit wide DDR2 memory bus.
The EVM uses two 1 gigabit 16 bit wide memories on this bus, for a total of 256
megabytes of memory for program, data, and video storage. The internal DDR
controller uses a PLL to control the DDR memory timing. The interface supports rates
up to 300 Mhz., and is clocked on differential edges for optimal performance. Memory
refresh for DDR2 is handled automatically by the TMS320DM6467 internal DDR
controller.
2.4 NAND Flash Interface
The TMS320DM6467 has 128 megabytes of NAND Flash mapped into the CS2 space.
The NAND Flash memory is used primarily for boot loading. The CS2 space is
configured as 8 bits wide on the TMS320DM6467 EVM for NAND flash usage.
The NAND and ATA interface are multiplexed with the PCI or daughter card interface.
The NAND and ATA interface can be active when the PCI or daughter card interfaces
are disabled.
2
C register implemented in the CPLD.
Spectrum Digital, Inc
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