Clock Circuitry; Reset Circuitry - Atmel SAM3N-EK User Manual

4.3.3

Clock Circuitry

The clock generator of a SAM3N microcontroller is made up of:
A Low Power 32,768 Hz Slow Clock Oscillator with bypass mode
A Low Power RC Oscillator
A 3 to 20 MHz Crystal Oscillator, which can be bypassed
A factory programmed fast internal RC Oscillator. 3 output frequencies can be selected: 4 (default
value), 8 or 12 MHz.
A 60 to 130 MHz programmable PLL (input from 3.5 to 20 MHz), capable to provide the clock MCK to
the processor and to the peripherals.
The SAM3N-EK board is equipped with one 12 MHz crystal, and one 32.768 Hz crystal. An optional
12 MHz Piezoelectric Ceramic Resonator can be mounted in place of the 12 MHz crystal (for low cost
clocking option evaluation).
Figure 4-3. SAM3N MCU
R1 R1 DNP DNP
C1 C1 15pF 15pF
3
Y1 Y1
Y2 Y2 12MHz 12MHz
DNP
DGND
C2 C2 15pF 15pF
R7 R7 DNP DNP
DGND
C3 C3
R5 R5
7pF 7pF
0R 0R
XIN32
Y3 Y3
32.768KHz 32.768KHz
DGND
XOUT32
R10 R10
C4 C4
7pF 7pF 0R 0R
NRST
4.3.4

Reset Circuitry

The on-board NRST button BP1 provides the SAM3N4C with external reset control.
Two User buttons BP2 and BP3, can be used to wake up the chip from low power modes.
The NRST pin is bidirectional. It is handled by the on-chip reset controller. It can be driven low to provide
a reset signal out to the external components. Conversely, it can be asserted low from the outside to
reset the microcontroller, its core and peripherals, with exception of the backup region (RTC, RTT and
SAM3N-EK Development Board User Guide
MN1 MN1
SAM3N4C-AU SAM3N4C-AU
R2 R2 0R 0R 97
XIN
PB9_XIN
R3 R3 0R 0R 96
XOUT
PB8_XOUT
7
PB2
PB2_URXD1_NPCS2_AD6
9
PB3
PB3_UTXD1_PCK2_AD7
88
PB10
PB10_DDM
89
PB11
PB11_DDP
JP1 JP1
+3V3 DNP DNP
JTAGSEL 77
JTAGSEL
PB4 51
PB4_TWD1_PWM2_TDI
PB6 79
PB6_TMS_SWDIO
83
PB7
PB7_TCK_SWCLK
76
PB5
PB5_TWCK1_TDO_TACESWO
NRST 60
NRST
PB0 3
PB0_PWM0_AD4
PB1 5
PB1_PWM1_AD5
JP3 JP3
+3V3
PB12 87
PB12_ERASE
61
TEST
VDDOUT VDDIN
VDDCORE
SAM3N - LQFP100 SAM3N - LQFP100
DGND
VDDPLL
DGND DGND
Evaluation Kit Hardware
PC[0..31]
74 PA0
PA0_PWM0_TIOA0
72 PA1
PA1_PWM1_TIOB0
67 PA2
PA2_PWM2_SCK0_DATRG
66
PA3
PA3_TWD0_NPCS3
55 PA4
PA4_TWCK0_TCLK0
53 PA5
PA5_RXD0_NPCS3
52
PA6
PA6_TXD0_PCKO
49
XIN32 R9 R9 DNP DNP PA7
PA7_RTS0_PWM3
48 XOUT32 R4 R4 DNP DNP PA8
PA8_CTS0_ADTRG
46
PA9
PA9_URXD0_NPCS1
44
PA10
PA10_UTXD0_NPCS2
42 PA11
PA11_NPCS0_PWM0
41 PA12
PA12_MISO_PWM1
33
PA13
PA13_MOSI_PWM2
31
PA14
PA14_SPCK_PWM3
30 PA15
PA15_TIOA1
28
PA16
PA16_TIOB1
12
PA17
PA17_PCK1_AD0
14
PA18
PA18_PCK2_AD1
18 PA19
PA19_AD2
24
PA20
PA20_AD3
15
PA21
PA21_RXD1_PCK1_AD8
20
PA22
PA22_TXD1_NPCS3_AD9
22 PA23
PA23_SCK1_PWM0
34
PA24
PA24_RTS1_PWM1
38
PA25
PA25_CTS1_PWM2
39 PA26
PA26_TIOA2
57 PA27
PA27_TIOB2
59
PA28
PA28_TCLK1
63 PA29
PA29_TCLK2
64 PA30
PA30_NPCS2
81
PA31
PA31_NPCS1_PCK2
1 ADVREF
ADVREF
93 PB13
PB13_PCK0_DAC0
99
PB14 C5 C5
PB14_NPCS1_PWM3
100nF 100nF
DGND
VDDIO
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB10
PB11
DGND
PB12
PB13
PB14
11080C–ATARM–30-Mar-11
PA[0..31]
+3V3
JP2 JP2
PB[0..14]
4-3