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Introduction
Symmetric Operations
– Transmit (TX) pins on the first device connect to the receive (RX) pins on the second device and
vice-versa.
– Data pin widths are automatically detected after reset
– Re-request packets, response packets, and flow control information are all multiplexed and sent
across the same physical pins.
– Supports both host/peripheral and peer-to-peer communication models
Simple block code packet formatting (8b/10b)
Supports in-band and flow control
– No extra pins are needed
– Allows the receiver to momentarily throttle the transmitter back when overflow is about to occur
– Uses the special built-in block code capability to interleave flow control information seamlessly with
user data
Automatic packet formatting optimizations
Internal loopback modes are provided
Connects to legacy VLYNQ devices
1.3
Functional Block Diagram
Figure 1
shows a functional block diagram of the VLYNQ port.
ARM/EDMA
System
memory
1.4
Industry Standard(s) Compliance Statement
VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard.
10
VLYNQ Port
Figure 1. VLYNQ Port Functional Block Diagram
Interface
VLYNQ register
access
CPU/EDMA initiated
transfers to
remote device
Interface
Off chip
(remote)
device access
VLYNQ module
Slave
VLYNQ_SCRUN
config
bus
VLYNQ_CLOCK
VLYNQ_TXD[3:0]
Master
VLYNQ_RXD[3:0]
config
bus
VLQINT
INT31
ARM interrupt
controller
www.ti.com
SPRUE36A – September 2007
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