Ich7-1 - EUROCOM M660N Service Manual

ICH7-1

SM_INTRUDER#
R180
+VDD5
1M
D12
R185 750 1% Z1401 R183 560 Z1402 A C
RB751V
R184
D10
2K 1%
RB751V
Z1403
R188
1K
INTVRMEN R7V1 R7V2
Z1404
JBAT1
C220 1
Enable(default) 1 STUFF UNSTUFF
1
2
2
*1UF
CON2_BAT
Disable 0 UNSTUFF STUFF
F950103
+VCCRTC
R509
332K_1%
Distance between the ICH7 M and
cap on the "P" signal should be
ICH_INTVRMEN
indentical distance between the
ICH7-M and cap on the "N"signal
R508 same pair.
*0
Short pins AH10 and AG10 at the
package.Place R7H1 winthin 500
mils of ICH7 BALL
+3VS
R492 10K SATALED#
R517 *1K ACZ_SDATAOUT
R99 4.7K IDE_PIORDY
RSVD9 15
R136
*1K
All manuals and user guides at all-guides.com
+VCCRTC
C542
10PF
Y4
Z1405 3 4 Z1406 R504
32.768KHZ 10M
U36A
+VCCRTC
C531 Z1407 AB1
RTCX1
10PF Z1408 AB2
RTCX2
R109 20K RTC_RST# AA3
RTCRST#
J4 SM_INTRUDER# Y5
INTRUDER#
C124 ICH_INTVRMEN W4
INTVRMEN
JOPEN
1UF Z1409 W1
EE_CS
Z1410 Y1
EE_SHCLK
Z1411 Y2
EE_DOUT
Z1412 W3
EE_DIN
Z1413 V3
LAN_CLK
Z1414 U3
LAN_RSTSYNC
Z1415 U5
LAN_RXD0
Z1416 V4
LAN_RXD1
Z1417 T5
LAN_RXD2
Z1418 U7
LAN_TXD0
Z1419 V6
LAN_TXD1
Z1420 V7
LAN_TXD2
ACZ_BITCLK R510 39 Z1421 U1
34 ACZ_BITCLK ACZ_BIT_CLK
ACZ_SYNC R132 39 Z1422 R6
34 ACZ_SYNC ACZ_SYNC
ACZ_RST# R519 39 Z1423 R5
34 ACZ_RST# ACZ_RST#
ACZ_SDATAIN0 R511 39 Z1424 T2
34 ACZ_SDATAIN0 ACZ_SDIN0
ACZ_SDATAIN1 R514 39 Z1425 T3
34 ACZ_SDATAIN1
ACZ_SDIN1
ACZ_SDATAIN2 T1
ACZ_SDIN2
ACZ_SDATAOUT R513 39 Z1426 T4
34 ACZ_SDATAOUT
ACZ_SDOUT
SATALED# AF18
27 SATALED#
SATALED#
AF3
18 SATARXN0
SATA0RXN
AE3
18 SATARXP0 SATA0RXP
C530 3900P Z1427 AG2
18 SATATXN0
SATA0TXN
C527 3900P Z1428 AH2
18 SATATXP0 SATA0TXP
AF7
SATA2RXN
AE7
SATA2RXP
Z1429 AG6
SATA2TXN
Z1430 AH6
SATA2TXP
CLK_PCIE_SATA# AF1
2 CLK_PCIE_SATA#
SATA_CLKN
CLK_PCIE_SATA AE1
2 CLK_PCIE_SATA SATA_CLKP
Z1431 AH10
SATARBIASN
R495 24.9_1% AG10
SATARBIASP
AF15
18 IDE_PDIOR#
DIOR#
AH15
18 IDE_PDIOW# DIOW#
AF16
18 IDE_PDDACK#
DDACK#
AH16
18 INT_IRQ14 IDEIRQ
IDE_PIORDY AG16
18 IDE_PIORDY
IORDY
AE15
18 IDE_PDDREQ DDREQ
ICH7-M
+1.05VS 2,3,4,5,9,17,32
+VDD5 23,26,27,29,30,32,34
+3VS 2,3,6,9,11,12,13,16,17,18,19,20,21,23,24,25,26,27,28,30,32,33,34
+3V 15,16,17,20,21,23,25,28,29,30,34
+VCCRTC 17
+3VH8 22,23,25,31,34
+5VS 16,17,18,22,23,24,25,27,29,30,32,33,34
LPC_AD[3:0] 23,26,33
AA6 LPC_AD0
LAD0
AB5 LPC_AD1
LAD1
AC4 LPC_AD2
LAD2
Y6 LPC_AD3
LAD3
AC3
LPC_DRQ#0 23,33
LDRQ0#
AA5 LPC_DRQ#1
LDRQ1#/GPIO23
AB3
LPC_FRAME# 23,26,33
LFRAME#
+1.05VS
AE22
H_A20GATE 23
A20GATE
AH28
H_A20M# 3
A20M#
AG27 Z1432 R485 *0
H_CPUSLP# 3,5
CPUSLP#
AF24 Z1433 R488 0
H_DPRSTP# 3,32
TP1/DPRSTP#
AH25 Z1434 R487 0
H_DPSLP# 3
TP2/DPSLP#
AG26 H_FERR#
FERR#
Z1437
AG24 R611 1K_0402
GPIO49/CPUPWRGD
AG22
H_IGNNE# 3
IGNNE#
AG21
FWH_INIT# 26
INIT3_3V#
AF22
INIT# H_INIT# 3
AF25
H_INTR 3
INTR
+1.05VS
AG23
RCIN# H_RCIN# 16,23
AH24 R489
H_NMI 3
NMI
AF23 Z1435 0 R104
H_SMI# 3
SMI#
AH22 56
H_STPCLK# 3
STPCLK#
AF26 Z1436 R486 24_1%
THERMTRIP# PM_THRMTRIP# 3,6,23
IDE_PDD[15:0] 18
AB15 IDE_PDD0
Layout note:R6V12
DD0
AE14 IDE_PDD1
needs to placed within
DD1
AG13 IDE_PDD2
DD2 2" of ich7.RV164 must
AF13 IDE_PDD3
DD3
be placed within 2" of
AD14 IDE_PDD4
DD4
AC13 IDE_PDD5 R6V12 W/O stub.
DD5
AD12 IDE_PDD6
DD6
AC12 IDE_PDD7
DD7
AE12 IDE_PDD8
DD8
AF12 IDE_PDD9
DD9
AB13 IDE_PDD10
DD10
AC14 IDE_PDD11
DD11
AF14 IDE_PDD12
DD12
AH13 IDE_PDD13
DD13
AH14 IDE_PDD14
DD14
AC15 IDE_PDD15
DD15
IDE_PDA[2:0] 18
AH17 IDE_PDA0
DA0
AE17 IDE_PDA1
DA1
AF17 IDE_PDA2
IDE
DA2
AE16
IDE_PDCS1# 18
DCS1#
AD16
DCS3# IDE_PDCS3# 18
Schematic Diagrams
Sheet 14 of 40
R105
56
ICH7-1
H_FERR# 3
H_PWRGD 3
C622
0.1U_04
ICH7-1 B - 15