Calistoga Strapping - EUROCOM M660N Service Manual

Schematic Diagrams

CALISTOGA STRAPPING

MCH_CFG_5
Sheet 11 of 40
CALISTOGA
STRAPPING
MCH_CFG_6
MCH_CFG_7
B - 12 CALISTOGA STRAPPING
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6 MCH_CFG_5
R63
*2.2K
MCH_CFG_9
LOW=DMIx2
(Def )
HI=DMIx4
6 MCH_CFG_6
R61
*2.2K
LOW=Moby Dick MCH_CFG_10 HOST
HI=Calistoga PLL VCC SELECT
(Def )
6 MCH_CFG_7
R65
*2.2K
LOW=RSVD MCH_CFG_11 PSB
HI=Mobile CPU (Def ) 4x CLK EANBLE
6 MCH_CFG_16
MCH_CFG_16(FSB LOW=Dynamic ODT Disable
Dynamic ODT) HI==Dynamic ODT Enable (Def )
+3VS 2,3,6,9,12,13,14,16,17,18,19,20,21,23,24,25,26,27,28,30,32,33,34
6 MCH_CFG_9
R86
*2.2K
LOW=Reverse Lane
HI=Normal operation
(Def )
6 MCH_CFG_10
R40
2.2K
LOW=Reverse Lane
HI=MOBILITY
6 MCH_CFG_11
MCH_CFG_20(PCIE
R64
Backward
Interpoerability
2.2K
LOW=Calistoga
mode)
HI=Reversed
R78
*2.2K
+3VS
(Def )
R47
MCH_CFG_18(VCC LOW=1.05V
SELECT) HI=1.5V (M660N)
1K
6 MCH_CFG_18
+3VS
(Def ) R45
MCH_CFG_19(DMI LOW=Normal
LANE REVERSAL) HI=LANES REVERSED
*1K
6 MCH_CFG_19
+3VS
LOW=only SVDO or PCIE x1 is
operational(defaults)
R34
HI=SVDO and PCIE x1 are
operation simultaneously
*1K
via the PEG port
6 MCH_CFG_20