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GOWIN GW1NSR Series User Manual

Package & pinout
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GW1NSR series of FPGA Products
Package & Pinout User Guide
UG823-1.5E, 10/18/2022

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Summary of Contents for GOWIN GW1NSR Series

  • Page 1 GW1NSR series of FPGA Products Package & Pinout User Guide UG823-1.5E, 10/18/2022...
  • Page 2 Copyright © 2022 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. and GOWIN are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 10/29/2018 1.0E Initial version published. 12/24/2018 1.1Ｅ IO bank description updated. 10/15/2019 1.2E Devices of GW1NSR-4/GW1NSR-4C added. 03/11/2020 1.3E MG64P package outline updated. The pin distribution view and pin number of GW1NSR-4/GW1NSR-4C 04/16/2020 1.4E QN48P updated. The package name of GW1NS-2/2C QN48 (PSRAM embedded) corrected 06/30/2020 1.4.1E...

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ..................... ii List of Tables ...................... iii 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Abbreviations and Terminology ................... 1 1.4 Support and Feedback ....................... 2 2 Overview ......................

  • Page 5: List Of Figures

    List of Figures List of Figures Figure 2-1 GW1NSR series I/O Bank Distribution ................7 Figure 3-2 View of GW1NSR-4C QN48P Pins Distribution (Top View) ..........10 Figure 3-3 View of GW1NSR-4C QN48G Pins Distribution (Top View) ..........11 Figure 3-4 View of GW1NSR-4/GW1NSR-4C MG64P Pins Distribution (Top View) ......12 Figure 4-2 Package Outline QN48P/QN48G ..................
  • Page 6 Table 2-2 GW1NSR Power Pins ......................4 Table 2-4 Quantity of GW1NSR-4/GW1NSR-4C Pins ............... 4 Table 2-5 Definition of the Pins in the GW1NSR series of FPGA products ........5 Table 3-2 Other Pins in GW1NSR-4C QN48P ................... 10 Table 3-3 Other Pins in GW1NSR-4C QN48G .................. 11 Table 3-4 Other Pins in GW1NSR-4/GW1NSR-4C MG64P ..............

  • Page 7: About This Guide

    1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose This manual contains an introduction to the GW1NSR series of FPGA products together with a definition of the pins, list of pin numbers, distribution of pins, and package diagrams. 1.2 Related Documents The latest user guides are available on the GOWINSEMI Website.

  • Page 8: Support And Feedback

    1 About This Guide 1.4 Support and Feedback 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below.

  • Page 9: Overview

    2.1 PB-Free Package The GW1NSR series of FPGA products are PB free in line with the EU ROHS environmental directives. The substances used in the GW1NSR series of FPGA products are in full compliance with the IPC-1752 standards.

  • Page 10: Power Pin

    2 Overview 2.3 Power Pin 2.3 Power Pin Table 2-2 GW1NSR Power Pins VCCO0 VCCO1 VCCO2 VCCO3 VCCX VCCPLL VCCP VDDA – 2.4 Pin Quantity 2.4.1 Quantity of GW1NSR-4/GW1NSR-4C Pins Table 2-3 Quantity of GW1NSR-4/GW1NSR-4C Pins GW1NSR-4/GW1NSR-4C Pin Type QN48P QN48G MG64P (GW1NSR-4C)

  • Page 11: Pin Definitions

    Table 2-4 provides a detailed overview of user I/O, multi-function pins, dedicated pins, and other pins. Table 2-4 Definition of the Pins in the GW1NSR series of FPGA products Pin Name Description Max. User I/O [End] indicates the pin location, including L(left) R(right) B(bottom), and T(top).
  • Page 12 2 Overview 2.5 Pin Definitions Pin Name Description currently; Low, the device cannot be programmed and configured currently. High, the programming configuration has been completed successfully; Low, the programming configuration has not been DONE completed or failed. When the DONE signal is low, delay the chip to activate. Activate the chip until the DONE signal is high.

  • Page 13: I/O Bank Introduction

    2.6 I/O BANK Introduction There are two I/O Banks in the GW1NSR series of FPGA products. The I/O BANK Distribution of the GW1NSR series of FPGA products is as shown in Figure 2-1. Figure 2-1 GW1NSR series I/O Bank Distribution...
  • Page 14 2 Overview 2.6 I/O BANK Introduction " " denotes VCC, VCCX, and VCCO. The filling color does not  change; " " denotes VSS, the filling color does not change;  " " denotes NC.  UG823-1.5E 8(15)

  • Page 15: View Of Pin Distribution

    3 View of Pin Distribution View of Pin Distribution UG823-1.5E 9(15)

  • Page 16: View Of Gw1Nsr-4/Gw1Nsr-4C Pins Distribution

    3 View of Pin Distribution 3.1 View of GW1NSR-4/GW1NSR-4C Pins Distribution 3.1 View of GW1NSR-4/GW1NSR-4C Pins Distribution 3.1.1 View of QN48P Pins Distribution Figure 3-1 View of GW1NSR-4C QN48P Pins Distribution (Top View) Table 3-1 Other Pins in GW1NSR-4C QN48P 11,37 VCCO0 VCCO1...

  • Page 17: View Of Qn48G Pins Distribution

    3 View of Pin Distribution 3.1 View of GW1NSR-4/GW1NSR-4C Pins Distribution 3.1.2 View of QN48G Pins Distribution Figure 3-2 View of GW1NSR-4C QN48G Pins Distribution (Top View) Table 3-2 Other Pins in GW1NSR-4C QN48G 11,37 VCCO0 VCCO1 VCCO2 VCCO3 12,24 VCCX UG823-1.5E 11(15)

  • Page 18: View Of Gw1Nsr-4/Gw1Nsr-4C Mg64P Pins Distribution

    3 View of Pin Distribution 3.1 View of GW1NSR-4/GW1NSR-4C Pins Distribution 3.1.3 View of GW1NSR-4/GW1NSR-4C MG64P Pins Distribution Figure 3-3 View of GW1NSR-4/GW1NSR-4C MG64P Pins Distribution (Top View) Table 3-3 Other Pins in GW1NSR-4/GW1NSR-4C MG64P VCCX VCCO0 VCCO1 VCCO2 VCCO3 D4,E5 UG823-1.5E 12(15)

  • Page 19: Package Diagrams

    4 Package Diagrams Package Diagrams UG823-1.5E 13(15)

  • Page 20: Gw1Nsr-4C Qn48P/Qn48G Package Outline (6Mm X 6Mm)

    4 Package Diagrams 4.1 GW1NSR-4C QN48P/QN48G Package Outline (6mm x 6mm) 4.1 GW1NSR-4C QN48P/QN48G Package Outline (6mm x 6mm) Figure 4-1 Package Outline QN48P/QN48G EXPOSED THERMAL PAD ZONE BOTTOM VIEW MILLIMETER SYMBOL 0.75 0.85 0.05 0.15 0.25 0.20 0.18 0.23 0.20 5.90 6.00...

  • Page 21: Gw1Nsr-4/Gw1Nsr-4C Mg64P Package Outline (4.2Mm X 4.2Mm)

    4 Package Diagrams 4.2 GW1NSR-4/GW1NSR-4C MG64P Package Outline (4.2mm x 4.2mm) 4.2 GW1NSR-4/GW1NSR-4C MG64P Package Outline (4.2mm x 4.2mm) Figure 4-2 Package Outline MG64P 1 2 3 4 5 6 7 8 UG823-1.5E 15(15)

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