Page 3
Revision History Date Version Description 10/24/2018 1.0E Initial version published. 01/10/2019 1.1E Introduction to the I/O BANK updated. I/O Bank View updated; 04/03/2019 1.2E CS16 package outline updated. 08/23/2019 1.3E The POD style of CS16 unified. 12/10/2019 1.4E The QN48 package information added.
Contents Contents Contents ......................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Abbreviations and Terminology ................... 1 1.4 Support and Feedback ....................... 2 2 Overview ......................
Page 5
Contents 4.2 FN32 Package Outline (4mm x 4mm) ................17 4.3 FN32F Package Outline (4mm x 4mm) ................19 4.4 QN48 Package Outline (6mm x 6mm, GW1NZ-1/2) ............21 4.5 CS100H Package Outline (4mm x 4mm) ................. 23 4.6 CG25 Package Outline (1.8mm x 1.8mm) ............... 25 4.7 FN24 Package Outline (3mm x 3mm) ................
List of Figures List of Figures Figure 3-1 View of GW1NZ-1 CS16 Pin Distribution (Top View) ............7 Figure 3-2 View of GW1NZ-1 FN32 Pin Distribution (Top View) ............8 Figure 3-3 View of GW1NZ-1 FN32F Pin Distribution (Top View) ............. 9 Figure 3-4 View of GW1NZ-1 QN48 Pin Distribution (Top View) ............
Page 7
List of Tables List of Tables Table 1-1 Abbreviations and Terminology ..................1 Table 2-1 Package and Max. User I/O Information ................3 Table 2-2 GW1NZ Power Pin ......................4 Table 2-3 Quantity of GW1NZ-1Pins ....................4 Table 3-1 Other Pins in GW1NZ-1 CS16 ................... 7 Table 3-2 Other Pins in GW1NZ-1 FN32 ...................
1 About This Guide 1.1 Purpose About This Guide 1.1 Purpose This manual contains an introduction to the GW1NZ series of FPGA products together with a definition of the pins, list of pin numbers, distribution of pins, and package diagrams. 1.2 Related Documents The latest user guides are available on the GOWINSEMI Website.
1 About This Guide 1.4 Support and Feedback 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below.
2.1 PB-Free Package The GW1NZ series of FPGA products are PB free in line with the EU ROHS environmental directives. The substances used in the GW1NZ series of FPGA products are in full compliance with the IPC-1752 standards.
2 Overview 2.3 Power Pin The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously. 2.3 Power Pin Table 2-2 GW1NZ Power Pin VCCIO0 VCCIO1...
This manual provides an overview of the distribution view of the pins in the GW1NZ series of FPGA products. Please refer to 3 View of Pin Distribution for further details. Different IO Banks in the GW1NZ series of FPGA products are marked with different colors.
3 View of Pin Distribution 3.1 View of GW1NZ-1 Pin Distribution View of Pin Distribution 3.1 View of GW1NZ-1 Pin Distribution 3.1.1 View of CS16 Pin distribution Figure 3-1 View of GW1NZ-1 CS16 Pin Distribution (Top View) Table 3-1 Other Pins in GW1NZ-1 CS16 VCCIO0 VCCIO1 VCCX...
3 View of Pin Distribution 3.1 View of GW1NZ-1 Pin Distribution 3.1.2 View of FN32 Pin Distribution Figure 3-2 View of GW1NZ-1 FN32 Pin Distribution (Top View) Table 3-2 Other Pins in GW1NZ-1 FN32 VCCIO0 VCCIO1 VCCX 8, 10 UG843-1.8.1E 8(27)
3 View of Pin Distribution 3.1 View of GW1NZ-1 Pin Distribution 3.1.3 View of FN32F Pin Distribution Figure 3-3 View of GW1NZ-1 FN32F Pin Distribution (Top View) Table 3-3 Other Pins in GW1NZ-1 FN32F VCCIO0 VCCIO1 VCCX 8、10 UG843-1.8.1E 9(27)
3 View of Pin Distribution 3.1 View of GW1NZ-1 Pin Distribution 3.1.4 View of QN48 Pin Distribution Figure 3-4 View of GW1NZ-1 QN48 Pin Distribution (Top View) Table 3-4 Other Pins in GW1NZ-1 QN48 12,37 VCCIO0 VCCIO1 VCCX 2,26 UG843-1.8.1E 10(27)
3 View of Pin Distribution 3.1 View of GW1NZ-1 Pin Distribution 3.1.5 View of CG25 Pin Distribution Figure 3-5 View of GW1NZ-1 CG25 Pin Distribution (Top View) Table 3-5 Other Pins in GW1NZ-1 CG25 VCCIO0 VCCIO1 VCCX UG843-1.8.1E 11(27)
3 View of Pin Distribution 3.1 View of GW1NZ-1 Pin Distribution 3.1.6 View of FN24 Pin Distribution Figure 3-6 View of GW1NZ-1 FN24 Pin Distribution (Top View) Table 3-6 Other Pins in GW1NZ-1 FN24 VCCIO0 VCCIO1 VCCX 12,17 UG843-1.8.1E 12(27)
3 View of Pin Distribution 3.2 View of GW1NZ-2 Pin Distribution 3.2 View of GW1NZ-2 Pin Distribution 3.2.1 View of QN48 Pin Distribution Figure 3-7 View of GW1NZ-2 QN48 Pin Distribution (Top View) Table 3-7 Other Pins in GW1NZ-2 QN48 VCCIO0 VCCIO1 VCCIO3/VCCIO4/VCCIO5...
3 View of Pin Distribution 3.2 View of GW1NZ-2 Pin Distribution 3.2.2 View of CS100H Pin Distribution Figure 3-8 View of GW1NZ-2 CS100H Pin Distribution (Top View) Table 3-8 Other pins in GW1NZ-2 CS100H VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCC/VCCPLL VCCD/VCCIOD VCCX...
Need help?
Do you have a question about the GW1NZ Series and is the answer not in the manual?
Questions and answers