GOWIN GW1NS-2C FPGA Development Board Manuals

Manuals and User Guides for GOWIN GW1NS-2C FPGA Development Board. We have 4 GOWIN GW1NS-2C FPGA Development Board manuals available for free PDF download: Programming And Configuration Manual, User Manual

GOWIN GW1NS-2C Programming And Configuration Manual (97 pages)

FPGA Products

Brand: GOWIN | Category: Semiconductors | Size: 1 MB

Table of Contents
4
List of Figures
6
About this Guide
10
Purpose
10
Related Documents
10
Terminology and Abbreviations
10
Table 1-1 Abbreviations and Terminology
10
Support and Feedback
11
Glossary
12
Table 2-1 Glossary
12
Configuration Modes
14
Littlebee ® Family of FPGA Products
14
Arora Family of FPGA Products
15
Table 3-1 Configuration Modes
15
Table 3-2 Configuration Modes
16
Configuration Pin
17
Configuration Pin List and Reuse Options
17
Configuration Pin List
17
Table 4-1 Configuration Pin List
17
Configuration Pin Multiplexing
18
Table 4-2 Pin Reuse Options
19
Configuration Pin Function and Application
20
Figure 4-1 Configuring Pin Reuse
20
Table 4-3 Pin Function
20
Figure 4-2 MCLK Frequency Setting
23
Configuration Mode Introduction
25
Configuration Notes
25
Figure 5-1 Recommended Pin Connection
27
Figure 5-2 Power Recycle Timing
27
JTAG Configuration
28
Figure 5-3 Trigger Timing
28
Table 5-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger
28
Table 5-2 Timing Parameters for Power-On Again and RECONFIG_N Triggering (Arora Family)
28
JTAG Configuration Mode Pins
29
Table 5-3 Pin Description in JTAG Configuration Mode
29
Connection Diagram for the JTAG Configuration Mode
30
Figure 5-4 Connection Diagram for JTAG Configuration Mode
30
JTAG Configuration Timing
31
Figure 5-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode
31
Figure 5-6 JTAG Configuration Timing
31
Table 5-4 JTAG Configuration Timing Parameters
31
JTAG Configuration Process
32
Figure 5-7 TAP State Machine
32
Figure 5-8 Instruction Register Access Timing
33
Figure 5-9 Data Register Access Timing
33
Table 5-5 Gowin FPGA IDCODE
34
Table 5-6 Change of TDI and TMS Value in the Process of Sending Instructions
34
Figure 5-10 Read Machine Flow Chart in ID Code State
35
Figure 5-11 the Access Timing of Read ID Code Instruction- 0X11
35
Figure 5-12 Read ID Code Data Register Access Timing
36
Figure 5-13 SRAM Configuration Flow
37
Table 5-7 Count of Address and Length of One Address
38
Figure 5-14 Process of Reading SRAM
39
Table 5-8 TCK Frequency Requirements for JTAG
40
Figure 5-15 the Embedded Flash Erasing Process of T Technology
41
Figure 5-16 the Embedded Flash Erasing Process of S Technology
43
Table 5-9 Readback-Pattern / Autoboot-Pattern
44
Figure 5-17 Process of Programming Internal Flash View
45
Figure 5-18 X-Page Programming
46
Figure 5-19 Y-Page Programming
47
Figure 5-20 Process of Reading Internal Flash
48
Figure 5-21 Process of Reading a Y-Page
49
Figure 5-22 GW1N-4 Background Programming Flow
50
Figure 5-23 Transfer JTAG Instruction Sample & Extest Flow Chart
51
Figure 5-24 Connection Diagram of JTAG Programming External Flash
52
Figure 5-25 Process View of Programming SPI Flash SPI
52
Figure 5-26 Timing Diagram of Sending 0X06 Via GW2A Series JTAG Simulating SPI
53
Figure 5-27 Timing Diagram of Sending 0X06 Via GW1N Series JTAG Simulating SPI
53
Table 5-10 Pin State
53
Figure 5-28 Process of Use Boundary Scan Mode to Program SPI Flash
54
Table 5-11 Status Register Definition
55
AUTO BOOT Configuration (Supported by Littlebee Family Only)
56
Figure 5-29 Connection Diagram of Daisy-Chain
56
Sspi
58
SSPI Mode Pins
58
Table 5-12 SSPI Mode Pins
58
SSPI Configuration Timing
59
Configuration Instruction
59
Figure 5-30 SSPI Configuration Timing
59
Table 5-13 SSPI Configuration Timing Parameters
59
Figure 5-31 Read ID Code Timing
60
Table 5-14 Configuration Instruction
60
Figure 5-32 Write Enable (0X15) Timing
61
Figure 5-33 Write Disable(0X3A00) Timing
61
Figure 5-34 Write Data (0X3B) Timing
62
Connection Diagram for SSPI Configuration Mode
63
Figure 5-35 SSPI Configuration Mode Connection Diagram
63
Figure 5-36 Connection Diagram of Programming External Flash Via SSPI
63
Figure 5-37 the Flow of Programming External Flash Via SSPI
64
Multiple FPGA Connection View in SSPI Mode
65
Mspi
65
Figure 5-38 Multiple FPGA Connection Diagram 1
65
Figure 5-39 Multiple FPGA Connection Diagram 2
65
Table 5-15 Pin Description in JTAG Configuration Mode
66
Figure 5-40 Connection Diagram for MSPI Configuration Mode
67
Figure 5-41 Connection Diagram of JTAG Programming External Flash
67
Figure 5-42 Input the Start Address for the Next Bitstream
68
Figure 5-43 Set the Programming Address for the External Flash
69
Figure 5-44 Connection Diagram for Configuring Multiple Fpgas Via Single Flash
70
Figure 5-45 MSPI Download Timing
70
DUAL BOOT Configuration (Supported by Littlebee Family Only)
71
Figure 5-46 Multiple FPGA Connection Diagram in MSPI Configuration Mode
71
Table 5-16 MSPI Configuration Timing Parameters
71
Figure 5-47 Dual Boot Flow Chart
72
CPU Mode
73
Table 5-17 CPU Mode Pins
73
Configuration Timing
74
SERIAL Mode
74
Figure 5-48 Connection Diagram for CPU Mode
74
Figure5-49 CPU Mode Configuration Timing
74
Figure 5-50 Connection Diagram for SERIAL Mode
75
Figure 5-51 SERIAL Configuration Timing
75
Table 5-18 Pin Definition in SERIAL Configuration Mode
75
I 2 C Mode
76
Table 5-19 SERIAL Configuration Timing Parameters
76
Table 5-20 Pin Definition in SERIAL Configuration Mode
76
Figure 5-52 Connection Diagram for I 2 C Mode
77
Figure 5-53 I 2 C Mode Timing
77
Table 5-21 I 2 C Configuration Timing Parameters
77
Bitstream File Configuration
79
Configuration Options
79
Configuration Data Encryption (Supported by Arora Family Only)
80
Definition
80
Figure 6-1 Configuration Options
80
Enter Encryption KEY
81
Enter the Decrypt Key
81
Figure 6-2 Encryption Key Setting Method
81
Programming Operation
82
Figure 6-3 Setting the Decryption Key
82
Figure 6-4 AES Security Configure
83
Programming Flow
84
Figure 6-5 Prepare
84
Figure6-6 Read AES Key Flow
85
Figure 6-7 Program AES Key Flow
86
Configuration File Size
87
Figure 6-8 Lock AES Key Flow
87
Configuration File Loading Time
88
Figure 6-9 Bitstream Format Generation
88
Table 6-1 Gowin FPGA Products Configuration File Size (Max.)
88
Table 6-2 Loading Frequency of Config File
89
Table 6-3 Loading Time in MSPI Mode
91
Table 6-4 Loading Time in Autoboot Mode
91
Safety Precautions
92
Boundary Scan
94
Figure 8-1 Boundary Scan Operation Schematic Diagram
95
SPI Flash Selection
96

GOWIN GW1NS-2C User Manual (36 pages)

Brand: GOWIN | Category: Semiconductors | Size: 1 MB

Table of Contents
4
List of Figures

6
1 About this Guide

8
2 Overview

10
3 View of Pin Distribution

18
4 Package Diagrams

27

GOWIN GW1NS-2C User Manual (23 pages)

Brand: GOWIN | Category: Receiver | Size: 0 MB

User Guide
1
Table of Contents
4
Contents

5
List of Figures

6
1 About this Manual

8
2 Function Introduction

10
- Overview
  10
- Features
  10
- Gowin UART Master IP
  10
- Gowin UART Slave IP
  10
3 Signal Definition

11
4 Working Principle

13
5 Interface Configuration

20

GOWIN GW1NS-2C User Manual (20 pages)

Brand: GOWIN | Category: Semiconductors | Size: 1 MB

Table of Contents
4
List of Figures
5
About this Guide
7
Purpose
7
Related Documents
7
Abbreviations and Terminology
7
Support and Feedback
7
Table 1-1 Abbreviations and Terminology
7
Overview
8
PB-Free Package
8
Package and Max. User I/O Information
8
Table 2-1 Package and Max. User I/O Information
8
Power Pins
9
Pin Quantity
9
Quantity of GW1NS-4/GW1NS-4C Pins
9
Table 2-2 GW1NS Power Pins
9
Table 2-3 Quantity of GW1NS-4/GW1NS-4C Pins
9
Pin Definitions
10
Table 2-4 Definition of the Pins in the GW1NS Series of FPGA Products
10
Introduction to the I/O BANK
12
Figure 2-1 GW1NS I/O Bank Distribution
12
View of Pin Distribution
14
View of GW1NS-4/GW1NS-4C Pins Distribution
14
View of CS49 Pins Distribution
14
Figure 3-1 View of GW1NS-4/GW1NS-4C CS49 Pins Distribution (Top View)
14
Table 3-1 Other Pins in GW1NS-4/GW1NS-4C CS49
14
View of QN48 Pins Distribution
15
Figure 3-2 View of GW1NS-4/GW1NS-4C QN48 Pins Distribution (Top View)
15
Table 3-2 Other Pins in GW1NS-4/GW1NS-4C QN48
15
View of MG64 Pins Distribution
16
Figure 3-3 View of GW1NS-4/GW1NS-4C MG64 Pins Distribution (Top View)
16
Table 3-3 Other Pins in GW1NS-4/GW1NS-4C MG64
16
Package Diagrams
17
CS49 Package Outline (2.9Mm X 2.9Mm)
17
Figure 4-1 Package Outline CS49
17
QN48 Package Outline (6Mm X 6Mm)
18
Figure 4-2 Package Outline QN48 (GW1NS-4 / GW1NS-4C)
18
MG64 Package Outline (4.2Mm X 4.2Mm)
19
Figure 4-3 MG64 Package Outline
19

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