National Instruments M Series User Manual page 262

Figure B-48 and Table B-32 show the setup and hold requirements at the PFI pins for the first
case (where a PFI pin drives Counter n Source and a different PFI pin drives Counter n Gate).
Figure B-48. Gate to Source Setup and Hold Timing Diagram
PFI (Gate)
PFI (Source)
Table B-32. Gate to Source Setup and Hold Timing
Time Description
t Setup time from PFI
8S
(Gate) to PFI
(Source)
t Hold time from PFI
8H
(Gate) to PFI
(Source)
Figure B-49 and Table B-33 show the setup and hold requirements of the internal block of the
DAQ-STC2. Use the table to calculate the setup and hold times for your Source and Gate signals
for the general case. In the general case, you can determine whether the setup and hold
requirements are met by adding up the various delays of the appropriate signals through the
counter/timer circuit.
Figure B-49. DAQ-STC2 Internal Block Setup and Hold Requirements Timing Diagram
Count_Enable
Selected_Source
Table B-33. DAQ-STC2 Internal Block Setup and Hold Requirements Timing
Time
t Setup
9S
t Hold
9H
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
t t
8S 8H
Gating Synchronizat
Mode ion Mode
Edge External
Source
Level External
Source
Edge External
Source
Level External
Source
t t
9S 9H
Parameter Min (ns)
1.5
0
M Series User Manual
Min (ns) Max (ns)
12.3 —
8.3 —
0.5 —
2.0 —
Max (ns)
—
—
© National Instruments | B-37