National Instruments M Series User Manual page 249

Appendix B Timing Diagrams
Figure B-28. Pause Trigger Input Delay Path
Signal_i
Logic
Sync Sample Clock Timebase
Figure B-29. Pause Trigger Timing Diagram
Selected Pause Trigger
Sync Sample Clock Timebase
Table B-17. Pause Trigger Timing from Signal_i to Selected Pause Trigger
Time From
t Signal_i
9
Table B-18. Pause Trigger Setup and Hold Timing
Time
t Setup
10
t Hold
11
Input Timing Verification
Consider an application that uses an external trigger and an external clock. The trigger and clock
signals are routed to an internal D flip-flop (DFF). To ensure that the trigger is sampled on a
particular clock edge, the setup and hold times of the internal DFF must be met:
• Recall that a "terminal" is a PFI pin, RTSI pin, or PXI_Star pin.
• Let TriggerDelay be the delay from the trigger terminal to the DFF.
• Let ClockDelay be the delay from the clock terminal to the DFF.
• Let DFF and DFF
Setup Hold
• Let External and External
Setup
the terminals.
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D Q
Selected Pause
Trigger
t
9
Signal_i
t
10
To
Selected Pause Trigger
Parameter Min (ns)
1.5
0
be the setup and hold time of the DFF.
be the setup and hold time of the trigger to the clock at
Hold
To Internal Logic
t
9
t
11
t
10
Min (ns) Max (ns)
1.7 7.8
Max (ns)
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