National Instruments M Series User Manual page 256

Table B-24. DO Timing Delays (Continued)
Time From
t DO Sample Clock
14
t DO Sample Clock
15
†
t PFI (output) high
16
*
The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the
trigger group for a given condition (maximum or minimum timing). This difference can be useful when
two external signals will be used together and the relative timing between the signals is important.
†
When DO Sample Clock is routed to a PFI output pin, the pulse width of the output is independent of
the pulse width of the input. The pulse width is specified in a number of periods of the 80 MHz Timebase.
Table B-25. DO Timing Requirements
Time Requirement
t PFI, RTSI, or
10
PXI_STAR
minimum period
t PFI, RTSI, or
11
PXI_STAR
minimum pulse
width
Counters Timing Diagrams
This section describes input delays, input requirements, output delays, gating modes, and
quadrature and two pulse encoder timing.
Input Delays
This section describes some of the timing delays of the counter/timer circuit. To describe delays
of the counter/timer, we model the circuitry as shown in Figure B-41. In the figure, PFI, RTSI,
and PXI_STAR represent signals at connectors pins of the M Series device. The other named
signals represent internal signals.
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To Min (ns)
P0 7.5
PFI (output) 8.0
PFI (output) Two periods of
low 80 MHz
Timebase
Condition Min (ms)
When used as NI 622x devices: 1000.0
DO Sample NI 625x/NI 628x
Clock devices: 100.0
When used as 12.0
DO Sample
Clock
M Series User Manual
Max (ns)
27.5
29.8
Three periods
of 80 MHz
Timebase
Max (ms)
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© National Instruments | B-31