Freescale Semiconductor MC9S12ZVHL64 Reference Manual

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S12 MagniV

Microcontrollers

MC9S12ZVHYRMV1

Rev. 1.05

6/2015

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Page 1 MC9S12ZVHY/MC9S12ZVHL Families Reference Manual S12 MagniV Microcontrollers MC9S12ZVHYRMV1 Rev. 1.05 6/2015 freescale.com...
Page 2 Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or...
Page 3: Table Of Contents
1.10.1 Features ............. . 60 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 4 3.1.1 Glossary ............. 116 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 5 External Signal Description ........... . . 145 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 6 6.5.4 Code Profiling ............228 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 7 7.7.3 Application Information for PLL and Oscillator Startup ......292 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 8 Interrupts ..............352 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 9 11.2.2 TXCAN — CAN Transmitter Output Pin ........424 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 10 12.5.5 Recovery from Stop Mode ..........514 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 11 14.7.1 IIC Programming Examples ..........562 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 12 16.6.1 Timer Counter Overflow Interrupt ......... 619 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 13 18.4.10RTC Minute Register (RTCMINR) ........649 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 14 20.3.4 Memory initialization ..........683 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 15 22.4 Functional Description ............749 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 16 B.1 ADC Operating Characteristics........... 789 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 17 K.2 Frequency Specifications ............815 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 18 Detailed Register Map............837 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 19 Appendix D IRC Electrical Specifications ......797 Appendix E LCD Electrical Specifications ......799 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 20 Appendix O Package Information ....... . 829 Appendix P Detailed Register Address Map......837 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 21 PAGE INTENTIONALLY LEFT BLANK S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 22 PAGE INTENTIONALLY LEFT BLANK S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 23: Introduction
In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 24: Features
8 ch (8-bit) / 4ch (16-bit) ADC Resolution 10-bit resolution 10-bit resolution 4 pins + internal 8 pins + internal 4 pins + internal 8 pins + internal ADC Inputs signals signals signals signals Frequency modulated PLL S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 25: Maskset 0N39G And 1N39G Device Compare
Up to 64 KB on-chip flash with ECC • 2 KB EEPROM with ECC • Up to 4 KB on-chip SRAM with ECC • Phase locked loop (IPLL) frequency multiplier with internal filter S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 26: Module Features
• Harvard Architecture - parallel data and code access • 3 stage pipeline • 32-Bit wide instruction and databus • 32-Bit ALU • 24-bit addressing, i.e. 16 MB linear address space S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 27: Embedded Memory
— Erase sector size 512 bytes — Automated program and erase algorithm — User margin level setting for reads — Protection scheme to prevent accidental program or erase S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 28: Clocks, Reset & Power Management Unit (Cpmu)
— Automatic frequency lock detector — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources: – Internal 1 MHz RC oscillator (IRC) – External 4-20 MHz crystal oscillator/resonator S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 29: Main External Oscillator (Xosclcp)
Unprogrammed byte value (0xFF) defaults to SWI instruction • ECC support on embedded NVM and SRAM 1.5.7 Real Time Clock (RTC) • Basic Clock functions with separate counters for Hour, Minutes and Seconds. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 30: Timer (Tim)
5 modes of operation allow for different display sizes to meet application requirements • Unused frontplane and backplane pins can be used as general-purpose I/O 1.5.12 LIN physical layer transceiver • Compliant with LIN physical layer 2.2 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 31: Stepper Motor Controller (Mc)
Three transmit buffers with internal prioritization using a “local priority” concept • Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, or either 8-bit filters • Programmable wake-up functionality with integrated low-pass filter S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 32: Inter-Ic Bus Module (Iic)
MSB-first or LSB-first shifting • Serial clock phase and polarity options 1.5.19 Analog-to-Digital Converter Module (ADC) • One ADC — 10-bit resolution — Up to 8 external channels & 8 internal channels S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 33: Supply Voltage Sensor (Bats)
— Power-On Reset (POR) — Low-Voltage Reset (LVR) — External ballast device support to reduce internal power dissipation — Capable of supplying both the MCU internally plus external components — Over-temperature interrupt S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 34: Block Diagram
Motor Driver0 SSD 0 PU[7:0] Motor Driver1 SSD 1 PD[7:0] PJ[3:0] TIM0 IOC0_[7:0] VLCD LINPHY PB[3:0] LGND LGND PA[7:0] 5V IO Supply VDDX3,2,1/VSSX3,2,1 VDDM1/VSSM1 VDDA/VSSA 1. LINPHY is only avaiable on ZVHL part S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 35: Device Memory Map
TIM1 0x0430-0x047F Reserved 0x0480-0x04AF 0x04B0-0x05BF Reserved 0x05C0-0x05EF TIM0 0x05F0-0x05FF Reserved 0x0600-0x063F ADC0 0x0640-0x06BF Reserved 0x06C0-0x06DF CPMU 0x06E0-0x06EF Reserved 0x06F0-0x06F7 BATS 0x06F8-0x06FF Reserved 0x0700-0x0707 SCI0 0x0708-0x070F Reserved 0x0710-0x0717 SCI1 0x0718-0x077F Reserved 0x0780-0x0787 SPI0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 36 Reserved register space shown in the table is not allocated to any module. This register space is reserved for future use. Writing to these locations has no effect. Read access to these locations returns zero. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 37 0x1F_C000 NVM IFR 256 Byte 0x20_0000 Unimplemented 6 MB 0x80_0000 Program NVM max. 8 MB Unimplemented address range Low address aligned High address aligned 0xFF_FFFF Figure 1-2. MC9S12ZVHY/MC9S12ZVHL Families Global Memory Map. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 38: Part Id Registers Assignments
0N39G 32’h03160000 MC9S12ZVHY64 1N39G 32’h03161000 MC9S12ZVHY32 1N39G 32’h03161000 MC9S12ZVHL64 1N39G 32’h03161001 MC9S12ZVHL32 1N39G 32’h03161001 Signal Description and Device Pinouts This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the individual IP blocks on the device.
Page 39: Detailed Signal Descriptions
PAD[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wake-up capability (KWAD[7:0]). These signals can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 40 PH[7:0] — Port H I/O Signals PH[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull-down devices are enabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 41 MISO0 Signal This signal is associated with the MISO functionality of the serial peripheral interface SPI0. This signal acts as master input during master mode or as slave output during slave mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 42 1.7.2.24 PWM[7:0] Signals The signals PWM[7:0] are associated with the PWM module digital channel outputs. 1.7.2.25 LCD Signals 1.7.2.25.1 FP[39:0] Signals These signals are associated with the segment LCD frontplane driver output. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 43 These signal are associated with the high current PWM out pin for the motor driver. 1.7.2.30 SSD[1:0] Signals 1.7.2.30.1 M0COSM, M0COSP, M0SINM and M0SINP Signals These signal are used to measure the back EMF to calibrate the pointer reset position which are associated with SSD[0]. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 44 RTC and LCD. Refer to Appendix Table K-2., “OSC32K Frequency Specifications for the startup time requirement. 32K OSC 32K_XTAL 32K_EXTAL Crystal or Resonator Figure 1-3. 32K OSC Crystal/Resonator Connection S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 45 1.7.2.34 LIN Physical Layer 0 Signals 1.7.2.34.1 This pad is connected to the single-wire LIN data bus. 1.7.2.34.2 LPTXD0 This is the LIN physical layer transmitter input signal. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 46: Vsense - Voltage Sensor Input
1.7.5.3 VDDM1, VSSM1 — External Power Supply Pins for Motor PAD These are the power supply and ground pins for the motor driver pads. It should be supply by external power transistor. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 47: Package And Pinouts
It must be protected externally against a reverse battery connection.VLINSUP is connected to VSUP on this device Package and Pinouts The MC9S12ZVHY/MC9S12ZVHL Families will be offered in 100 pin and 144 pin LQFP packages. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 48 VSS1 KWT6 / IOC1_6 / ECLK / PT6 FP22 / PF6 FP21 / PF5 FP20 / PF4 FP19 / PF3 FP18 / PF2 VSUP Figure 1-4. MC9S12ZVHY/MC9S12ZVHL Families 144-pin LQFP pin out S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 49 KWT6 / IOC1_6 / ECLK / PT6 BCTL FP22 / PF6 VSENSE FP21 / PF5 VSS1 FP20 / PF4 FP19 / PF3 FP18 / PF2 VSUP Figure 1-5. MC9S12ZVHY 100-pin LQFP pin out S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 50 Figure 1-6. MC9S12ZVHL 100-pin LQFP pin out Table 1-7. Pin Summary LQFP Internal Pull Function Option Resistor Power Supply Reset CTRL Func. Func. Func. Func. Func. State FP26 — — — — VDDX PERG/ Pull PPSG Down S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 51 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 52 PPSD Down FP13 — — — — VDDX PERD/ Pull PPSD Down FP12 — — — — VDDX PERD/ Pull PPSD Down FP11 — — — — VDDX PERD/ Pull PPSD Down S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 53 PERP/ Disabled PPSP — — — — — — — — — — — — — — — — — — — — — RXCAN0 — — — — PERC/ Disabled PPSC S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 54 — — — — — — — — VDDX PERJ/ Disabled PPSJ — — — — — — — — — — — — — — — — — — — — S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 55 PPST DBGEEV IOC1_2 KWT2 — — PERT/ Disabled PPST PDOCLK IOC1_3 KWT3 — — PERT/ Disabled PPST IOC1_2 KWT2 — — PERT/ Disabled PPST SGT0 IOC0_6 — — — PERC/ Disabled PPSC S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 56 — — PERE/ Pull PPSE Down VSS2 — — — — — — — — — — — — — — — — — PWM0 — — — — PERP/ Disabled PPSP S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 57 PPSH Down FP31 — — — — VDDX PERG/ Pull PPSG Down FP30 — — — — VDDX PERG/ Pull PPSG Down FP29 — — — — VDDX PERG/ Pull PPSG Down S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 58: Modes Of Operation
This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). The processor program is executed from internal memory. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 59: Debugging Modes
— The oscillator is stopped in this mode. By default, clocks are switched off and the counters and dividers remain frozen. The Autonomous Periodic Interrupt (API), Key Wake-Up, RTC, CAN and the CAN physical layer transceiver modules may be enabled to wake the device. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 60: Security
SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 61: Operation Of The Secured Microcontroller
In normal single chip mode, security can be temporarily disabled using the backdoor key access method. This method requires that: • The backdoor key has been programmed to a valid value. • The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 62: Reprogramming The Security Bits
Resets and Interrupts 1.11.1 Resets Table 1-10. lists all reset sources and the vector locations. Resets are explained in detail in the Chapter 7, “S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)”. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 63: Interrupt Vectors
TIM0 timer channel 5 I bit TIM0TIE (C5I) Vector base + 0x1B4 TIM0 timer channel 6 I bit TIM0TIE (C6I) Vector base + 0x1B0 TIM0 timer channel 7 I bit TIM0TIE (C7I) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 64 Vector base + 0x144 LINPHY0 over-current interrupt I bit LP0IE (LP0ERR) Vector base + 0x140 BATS supply voltage monitor interrupt I bit BATIE (BVHIE,BVLIE) Vector base + 0x13C Reserved Vector base + 0x130 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 65 Motor Control Timer Overflow I bit MCCTL1(MCOCIE) Vector base + 0x74 SSD0 I bit MDC0CTL(MCZIE,AOVIE) Vector base + 0x70 SSD1 I bit MDC1CTL(MCZIE,AOVIE) Vector base + 0x6C Reserved Vector base + 0x68 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 66: Effects Of Reset
All other RAM arrays are not initialized out of any type of reset. With the exception of resets resulting from low voltage conditions, the RAM content is unaltered by a reset occurrence. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 67: Cop Configuration
COPCTL Register Table 1-13. Initial WCOP Configuration NV[3] in WCOP in FOPT Register COPCTL Register 1.13 ADC0 Internal Channels Table 1-14 lists the internal sources which are connected to these special conversion channels. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 68: The Adc0 Vrh/Vrl
NVM’s IFR for reference.The measurement conditions of the reference conversion are listed in Section A.1.10, “ADC Conversion Result Reference””. By measuring the voltage V (see Table 1-14) 1. The format of the stored V reference value is still subject to change. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 69: Bdc Clock Source Connectivity
And if select the 1 MHz internal IRC clock, then the clock will be off when enter full stop or pseudo stop mode, the RTC function will be stop. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 70: Lcd Clock Source Connectivity
(RTCCTL2)”. Setting the bits to 2’b01 enable the 32K OSC, it also selects the 32K OSC as the source for LCD and RTC clock. RTCCTL2 is write one time only in NSC mode, once enable the 32K OSC, it will be not able to switch off. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 71: Introduction
8-pin port G associated with LCD FP[31:24] • 8-pin port H associated with LCD FP[39:32] • 4-pin Port J • 8-pin port P associated with 8 PWM channels; associated with the rerouting SCI1 function also. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 72: Features
— rerouting the RTC_CAL to TIM1 channel — rerouting the RXD0 and RXD1 to TIM1 channel for the baud rate detection — Various SCI0-LINPHY0 routing options supporting standalone use and conformance testing S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 73: External Signal Description
(lowest priority). Table 2-1. Pin Functions and Priorities Pin Function Port Pin Name Description Routing Register Function & Priority after Reset BKGD MODC MODC input during RESET BKGD BKGD I/O S12ZBDC communication S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 74 PTA[0] I/O General-purpose O LCD BP3 signals GPIO PTB[3] I/O General-purpose O LCD BP2 signal PTB[2] I/O General-purpose O LCD BP1 signal PTB[1] I/O General-purpose O LCD BP0 signal PTB[0] I/O General-purpose S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 75 I/O General-purpose FP11 O LCD FP11 signal PTD[3] I/O General-purpose FP10 O LCD FP10 signal PTD[2] I/O General-purpose O LCD FP9 signal PTD[1] I/O General-purpose O LCD FP8 signal PTD[0] I/O General-purpose S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 76 FP19 O LCD FP19 signal PTF[3] I/O General-purpose FP18 O LCD FP18 signal PTF[2] I/O General-purpose FP17 O LCD FP17 signal PTF[1] I/O General-purpose FP16 O LCD FP16 signal PTF[0] I/O General-purpose S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 77 PTH[2] I/O General-purpose FP33 O LCD FP33 signal PTH[1] I/O General-purpose FP32 O LCD FP32 signal PTH[0] I/O General-purpose PTJ[3] I/O General-purpose GPIO PTJ[2] I/O General-purpose PTJ[1] I/O General-purpose PTJ[0] I/O General-purpose S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 78 PWM3 O PWM channel 3 PP[3] I/O General-purpose PWM2 O PWM channel 2 PP[2] I/O General-purpose PWM1 O PWM channel 1 PP[1] I/O General-purpose PWM0 O PWM channel 0 PP[0] I/O General-purpose S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 79 I/O General-purpose; with interrupt and wakeup MOSI0 I/O SPI0 master out/slave in PTS[1]/KWS[1] I/O General-purpose; with interrupt and wakeup MISO0 I/O SPI0 master in/slave out PTS[0]/KWS[0] I/O General-purpose; with interrupt and wakeup S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 80 I/O RTC CALCLK output or external 1HZ input PTT[1]/KWT[1] I/O General-purpose; with interrupt and wakeup (IOC1_0) I/O TIM1 channel 0 T1IC0RR1-0 API_EXTCLK O API clock output PTT[0]/KWT[0] I/O General-purpose; with interrupt and wakeup S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 81 I/O General-purpose; with interrupt and wakeup KWADL[2] PAD1 AN0_1 ADC0 analog input 1 PTADL[1]/ I/O General-purpose; with interrupt and wakeup KWADL[1] PAD0 AN0_0 ADC0 analog input 0 PTADL[0]/ I/O General-purpose; with interrupt and wakeup KWADL[0] S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 82: Memory Map And Register Definition
A stop or wait recovery with the X bit set (refer to S12ZCPU reference manual) is not available. Memory Map and Register Definition This section provides a detailed description of all port integration module registers. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 83: Register Map
Reserved Reserved Reserved Reserved Reserved 0x0210– Reserved 0x021F 0x0220 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 0x0221 PTB3 PTB2 PTB1 PTB0 PTIA7 PTIA6 PTIA5 PTIA4 PTIA3 PTIA2 PTIA1 PTIA0 0x0222 PTIA S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 84 0x0242 PTIC PTID7 PTID6 PTID5 PTID4 PTID3 PTID2 PTID1 PTID0 0x0243 PTID 0x0244 DDRC DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0x0245 DDRD DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 85 PERE2 PERE1 PERE0 0x0267 PERF PERF7 PERF6 PERF5 PERF4 PERF3 PERF2 PERF1 PERF0 0x0268 PPSE PPSE3 PPSE2 PPSE1 PPSE0 0x0269 PPSF PPSF7 PPSF6 PPSF5 PPSF4 PPSF3 PPSF2 PPSF1 PPSF0 0x026A– Reserved 0x027F S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 86 PPSADL7 PPSADL6 PPSADL5 PPSADL4 PPSADL3 PPSADL2 PPSADL1 PPSADL0 0x028A– Reserved 0x028B 0x028C Reserved 0x028D PIEADL PIEADL7 PIEADL6 PIEADL5 PIEADL4 PIEADL3 PIEADL2 PIEADL1 PIEADL0 0x028E Reserved 0x028F PIFADL PIFADL7 PIFADL6 PIFADL5 PIFADL4 PIFADL3 PIFADL2 PIFADL1 PIFADL0 0x0290– Reserved 0x0298 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 87 0x02D1 PTIS 0x02D2 DDRS DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0x02D3 PERS PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 0x02D4 PPSS PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 88 PTH1 PTH0 PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 0x0301 PTIH 0x0302 DDRH DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 0x0303 PERH PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 89 0x0324 PPSG PPSG7 PPSG6 PPSG5 PPSG4 PPSG3 PPSG2 PPSG1 PPSG0 0x0325– Reserved 0x032F 0x0350 PTU7 PTU6 PTU5 PTU4 PTU3 PTU2 PTU1 PTU0 PTIU7 PTIU6 PTIU5 PTIU4 PTIU3 PTIU2 PTIU1 PTIU0 0x0351 PTIU S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 90: Register Descriptions
The description of registers PTx, PTIx, DDRx, DIENx, PERx, PPSx, SRRx, WOMx, PIEx and PIFx generically assumes a fully implemented 8-bit register. For availability of individual bits refer Section 2.3.1, “Register Map“”. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 91 Field Description Module Routing Register — PWM6 routing PWM6RR 1 PWM6 to PA7 0 PWM6 to PP6 Module Routing Register — PWM4 routing PWM4RR 1 PWM4 to PA6 0 PWM4 to PP4 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 92 11 TIM1 input capture channel 0 is connected to RXD1 10 TIM1 input capture channel 0 is connected to RXD0 01 TIM1 input capture channel 0 is connected to RTC’s CALCLK 00 TIM1 input capture channel 0 is connected to PT0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 93 SCI0 must be enabled for TXD0 routing to take effect on pins. LINPHY0 must be enabled for LPRXD0 and LPDC0 routings to take effect on pins. 1. This register is only avaiable on ZVHL S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 94 SCI0 connects to LINPHY0, interface accessible on 2 external pins TXD0 -> PS7 Conformance test setting: PC3 -> LPTXD0 PS6 -> RXD0 Interface opened and all 4 signals routed externally LPRXD0 -> PC2 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 95 IRQ Control Register (IRQCR) Address 0x0209 Access: User read/write IRQE IRQEN Reset Figure 2-7. IRQ Control Register (IRQCR) 1. Read: Anytime Write: IRQE: Once in normal mode, anytime in special mode IRQEN: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 96 Table 2-8. PIM Miscellaneous Register Field Descriptions Field Description RTC_CAL output Enable — Activate the RTC CALCLK output on PT1 CALCLKE 1 CALCLK output on PT1 enabled 0 CALCLK output on PT1 disabled S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 97 Port C Polarity Select Register Address 0x0248 PPSC Access: User read/write PPSx7 PPSx6 PPSx5 PPSx4 PPSx3 PPSx2 PPSx1 PPSx0 Reset Figure 2-11. Port C Polarity Select Register 1. Read: Anytime Write: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 98 Port S Polarity Select Register Address 0x02D4 PPSS Access: User read/write PPSx7 PPSx6 PPSx5 PPSx4 PPSx3 PPSx2 PPSx1 PPSx0 Reset Figure 2-12. Port S Polarity Select Register 1. Read: Anytime Write: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 99 0x0320 PTG 0x0350 PTU PTx7 PTx6 PTx5 PTx4 PTx3 PTx2 PTx1 PTx0 Reset Figure 2-13. Port Data Register 1. Read: Anytime. The data source is depending on the data direction value. Write: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 100 Port Input — Data input PTIx A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 101 2-22). If more then one peripheral function is available and enabled at the same time, the highest ranked module according the predefined priority scheme in Table 2-1 will take precedence on the pin. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 102 If the pin is used with an analog function this bit shall be cleared to avoid shoot-through current. 1 Associated pin is configured as digital input 0 Associated pin digital input is disabled S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 103 The polarity is selected by the related polarity select register bit. On open- drain output pins only a pullup device can be enabled. 1 Pull device enabled 0 Pull device disabled S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 104 If MSCAN0 is active a pullup device can be activated on the RXCAN0 input; attempting to select a pulldown disables the pull-device. 1 Pulldown device selected; rising edge selected 0 Pullup device selected; falling edge selected S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 105 This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. 1 Interrupt is enabled 0 Interrupt is disabled (interrupt flag masked) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 106 Description Port Slew Rate— Slew Rate control SRRx 1 Enable the slew rate control and disable the digital input buffer 0 Disable the slew rate control and enable the digital input buffer S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 107: Functional Description
For example selecting a pullup device: This device does not become active while the port is used as a push- pull output. Table 2-21. Register availability per port Slew Data Pull Polarity Wired- Interrupt Interrupt Port Data Input Rate Direction Enable Select Or Mode Enable Flag Enable S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 108 Forced off if output MxSINM, MxSINP API_EXTCLK Forced output Forced off ADCx None (DDR maintains None (PER/PPS maintain control) control LINPHYx LPTXD0 Forced input None (PER/PPS maintain control) LPRXD0 Forced output Forced off S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 109 Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on port data or port input registers, when changing the data direction register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 110 If the pin is used as an output this register turns off the active-high drive. This allows wired-or type connections of outputs. 2.4.2.7 Interrupt enable register (PIEx) If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 111: Interrupts
IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register. The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN] is cleared while an interrupt is pending, the request will deassert. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 112: Pin Interrupts And Wakeup
Sample count <= 4 (at active or passive level) and interrupt flag not set (PIF[x]=0). Glitch, filtered out, no interrupt flag set uncertain Valid pulse, interrupt flag set P_MASK P_PASS Figure 2-25. Interrupt Glitch Filter (here: active low level selected) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 113: Initialization And Application Information
The off chip RTC calibration, user need to set the CALCLKEN bit in the PIMMIC register to enable the CALCLK out on RTC_CAL pin. Base on the external requirement, user can set the RTCMOD and CALS bit in RTCCTL3 registers to get the expected CALCLK output on RTC_CAL pin. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 114 Chapter 2 Port Integration Module (S12ZVHYPIMV1) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 115: Introduction
S12ZBDC module. It also provides dirct memory access for the ADC module. The S12ZMMC determines the address mapping of the on-chip resources, regulates access priorities and enforces memory protection. Figure 3-1 shows a block diagram of the S12ZMMC module. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 116: Glossary
The S12ZMMC determines the chip configuration mode of the device. It captures the state of the MODC pin at reset and provides the ability to switch from special-single chip mode to normal single chip-mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 117: Block Diagram
3.3.1 Memory Map A summary of the registers associated with the MMC block is shown in Figure 3-2. Detailed descriptions of the registers and bits are given in the subsections that follow. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 118: Register Descriptions
0x0087 MMCPCL CPUPC[7:0] 0x0088- Reserved 0x00FF = Unimplemented or Reserved Figure 3-2. S12ZMMC Register Summary 3.3.2 Register Descriptions This section consists of the S12ZMMC control and status register descriptions in address order. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 119 Reset with Reset with MODC pin = 1 MODC pin = 0 Normal Special Single-Chip Single-Chip Mode (NS) write access to Mode (SS) MODE: 1  MODC bit Figure 3-4. Mode Transition Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 120 Target Field — The TGT[3:0] bits capture the target of the faulty access. The target is captured in form of a (MMCECH) TGT[3:0] 4 bit value which is assigned as follows: none register space EEPROM program flash 6-15: reserved S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 121 3.3.2.3 Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL) Address: 0x0082 (MMCCCRH) CPUU Reset Address: 0x0083 (MMCCCRL) CPUX CPUI Reset Figure 3-6. Captured S12ZCPU Condition Code Register (MMCCCRH, MMCCCRL) Read: Anytime Write: Never S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 122 Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL) Address: 0x0085 (MMCPCH) CPUPC[23:16] Reset Address: 0x0086 (MMCPCM) CPUPC[15:8] Reset Address: 0x0087 (MMCPCL) CPUPC[7:0] Reset Figure 3-7. Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL) Read: Anytime Write: Never S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 123: Functional Description
The S12ZMMC maps all on-chip resources into an 16MB address space, the global memory map. The exact resource mapping is shown in Figure 3-8. The global address space is used by the S12ZCPU, ADC, and the S12ZBDC module. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 124 6 KBKB 0x1F_C000 NVM IFR 256 Byte 0x20_0000 Unmapped 6 MByte 0x80_0000 Program NVM max. 8 MByte Unmapped address range Low address aligned High address aligned 0xFF_FFFF Figure 3-8. Global Memory Map S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 125: Illegal Accesses
Illegal accesses are reported in several ways: • All illegal accesses performed by the S12ZCPU trigger machine exceptions. • All illegal accesses performed through the S12ZBDC interface, are captured in the ILLACC bit of the BDCCSRL register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 126: Uncorrectable Ecc Faults
S12ZCPU or ADC access triggers a machine exception. Uncorrectable memory corruptions which are detected during a S12ZBDC access, are captured in the RAMWF or the RDINV bit of the BDCCSRL register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 127: Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to the CPU. The INT module supports: • I-bit and X-bit maskable interrupt requests • One non-maskable unimplemented page1 op-code trap S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 128: Glossary
1. The vector base is a 24-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as the upper 15 bits of the address) and 0x000 (used as the lower 9 bits of the address). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 129: Modes Of Operation
In stop mode, the INT module is capable of waking up the CPU if an eligible CPU exception occurs. Please refer to Section 4.5.3, “Wake Up from Stop or Wait Mode” for details. 4.1.4 Block Diagram Figure 4-1 shows a block diagram of the INT module. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 130: External Signal Description
INT module registers. Table 4-3. INT Memory Map Address Access 0x000010–0x000011 Interrupt Vector Base Register (IVBR) 0x000012–0x000016 RESERVED — 0x000017 Interrupt Request Configuration Address Register (INT_CFADDR) 0x000018 Interrupt Request Configuration Data Register 0 (INT_CFDATA0) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 131: Register Descriptions
0x000017 INT_CFADDR R INT_CFADDR[6:3] 0x000018 INT_CFDATA0 R PRIOLVL[2:0] 0x000019 INT_CFDATA1 R PRIOLVL[2:0] 0x00001A INT_CFDATA2 R PRIOLVL[2:0] 0x00001B INT_CFDATA3 R PRIOLVL[2:0] 0x00001C INT_CFDATA4 R PRIOLVL[2:0] = Unimplemented or Reserved Figure 4-2. INT Register Summary S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 132 Therefore, changing the IVBR has no effect on the location of the reset vector (0xFFFFFC–0xFFFFFF). 4.3.2.2 Interrupt Request Configuration Address Register (INT_CFADDR) Address: 0x000017 INT_CFADDR[6:3] Reset = Unimplemented or Reserved Figure 4-4. Interrupt Configuration Address Register (INT_CFADDR) Read: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 133 Figure 4-6. Interrupt Request Configuration Data Register 1 (INT_CFDATA1) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001A PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-7. Interrupt Request Configuration Data Register 2 (INT_CFDATA2) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 134 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x00001E PRIOLVL[2:0] Reset = Unimplemented or Reserved Figure 4-11. Interrupt Request Configuration Data Register 6 (INT_CFDATA6) 1. Please refer to the notes following the PRIOLVL[2:0] description below. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 135: Functional Description
The INT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 136: S12Z Exception Requests
CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored from the stack by executing the RTI instruction. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 137: Priority Decoder
(Vector base + 0x0001F4) Unimplemented page2 op-code trap (TRAP) vector request (Vector base + 0x0001F0) Software interrupt instruction (SWI) vector request (Vector base + 0x0001EC) System call interrupt instruction (SYS) vector request S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 138: Interrupt Vector Table Layout
I-bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority, so that there can be up to seven nested I-bit maskable interrupt requests at a time (refer to Figure 4- for an example using up to three nested interrupt requests). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 139: Wake Up From Stop Or Wait Mode
The X-bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the X-bit in CCW is set . If the X-bit maskable interrupt request is used to wake-up the MCU with the X- S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 140 1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is shared with other peripheral modules on the device. Please refer to the Port Integration Module (PIM) section of the MCU reference manual for details. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 141: Introduction
Normal Single Chip Mode (device operating mode) BDCSI Background Debug Controller Serial Interface. This refers to the single pin BKGD serial interface. EWAIT Optional S12 feature which allows external devices to delay external accesses until deassertion of EWAIT S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 142: Features
When operating in secure mode, BDC operation is restricted to allow checking and clearing security by mass erasing the on-chip flash memory. Secure operation prevents BDC access to on-chip memory other than mass erase. The BDC command set is restricted to those commands classified as Always-available. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 143 If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stop exception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the host attempts further communication before the ACK pulse generation then the OVRUN bit is set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 144: Block Diagram
If the part is still in Wait mode and a further STEP1 is carried out then the NORESP and ILLCMD bits are set because the device is no longer in active BDM for the duration of WAI execution. 5.1.4 Block Diagram A block diagram of the BDC is shown in Figure 5-1. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 145: External Signal Description
Memory Map and Register Definition 5.3.1 Module Memory Map Table 5-4 shows the BDC memory map. Table 5-4. BDC Memory Map Size Global Address Module (Bytes) Not Applicable BDC registers S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 146: Register Descriptions
— Bit 5 can only be written by WRITE_BDCCSR commands when the device is not in stop mode. — Bits 6, 1 and 0 cannot be written. They can only be updated by internal hardware. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 147 Reading this bit indicates the status of the requested mass erase sequence. 0 No flash mass erase sequence pending completion 1 Flash mass erase sequence pending completion. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 148 RAM Write Fault — Indicates an ECC double fault during a BDC write access to RAM. RAMWF Writing a “1” to this bit, clears the bit. 0 No RAM write double fault detected. 1 RAM write double fault detected. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 149 (Section 5.4.5.1). Illegal accesses return a value of 0xEE for each data byte Writing a “1” to this bit, clears the bit. 0 No illegal access detected. 1 Illegal BDC access detected. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 150: Functional Description
After resetting into SSC mode, the initial PC address must be supplied by the host using the WRITE_Rn command before issuing the GO command. 1. BDM active immediately out of special single-chip reset. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 151: Clock Source
BDCSI Clock and FSM BDCFCLK CLKSW BDC device resource interface Core clock Figure 5-5. Clock Switch 5.4.4 BDC Commands BDC commands can be classified into three types as shown in Table 5-7. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 152 BDC shift register before the write has been completed. The external host must wait at least for 16 bdcsi cycles after a control command before starting any new serial command. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 153 ACK_ENABLE Always 0x02/dack Enable the communication handshake. Available Issues an ACK pulse after the command is executed. BACKGROUND Non-Intrusive 0x04/dack Halt the CPU if ENBDC is set. Otherwise, ignore as illegal command. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 154 READ_MEM.sz_WS Non-Intrusive (0x31+4 x sz)/ad24/d/ss/rd.sz Read the appropriately-sized (sz) memory value from the location specified by the 24- bit address and report status READ_DBGTB Non-Intrusive (0x07)/dack/rd32/dack/rd32 Read 64-bits of DBG trace buffer S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 155: Classification
BDCSI clock). 4. Removes all drive to the BKGD pin so it reverts to high impedance. 5. Listens to the BKGD pin for the sync response pulse. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 156 (ACK) pulse issued by the target MCU in response to a host command. The ACK_ENABLE command is interpreted and executed in the BDC logic without the need to interface S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 157 BDMACT is clear. Whilst in wait mode, with the pending BDM request, non-intrusive BDC commands are allowed. 5.4.4.5 DUMP_MEM.sz, DUMP_MEM.sz_WS DUMP_MEM.sz Read memory specified by debug address register, then Non-intrusive increment address 0x32 Data[7-0] S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 158: Dump_Mem.sz
If enabled, an ACK pulse is driven before the data bytes are transmitted. The effect of the access size and alignment on the next address to be accessed is explained in more detail in Section 5.4.5.2”. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 159: Fill_Mem.sz
0x13 Data[7-0] BDCCSRL host  host  target  target target host 0x17 Data[15-8] Data[7-0] BDCCSRL host  host  host  target  target target target host S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 160 If enabled, an ACK is driven on exiting active BDM. If a GO command is issued whilst the BDM is inactive, an illegal command response is returned and the ILLCMD bit is set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 161: Go_Until
This command reads the selected CPU registers and returns the 32-bit result. Accesses to CPU registers are always 32-bits wide, regardless of implemented register width. Bytes that are not implemented return S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 162: Read_Mem.sz
 target  target target host host host host host Read data at the specified memory address. The address is transmitted as three 8-bit packets (msb to lsb) immediately after the command. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 163: Read_Dbgtb
READ_SAME.sz, READ_SAME.sz_WS READ_SAME Read same location specified by previous READ_MEM{_WS} Non-intrusive 0x54 Data[15-8] Data[7-0] host  target  target  target host host READ_SAME_WS Read same location specified by previous READ_MEM{_WS} Non-intrusive S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 164 STOP instruction with BDCCIS clear, or if a CPU access is delayed by EWAIT. If the CPU is executing the STOP instruction and BDCCIS is set, then SYNC_PC returns the PC address of the instruction following STOP in the code listing. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 165 If the with-status option is specified, the status byte contained in BDCCSRL is returned after the write data. This status byte reflects the state after the memory write was performed. The examples show the S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 166 Mass erase the internal flash. This command can always be issued. On receiving this command twice in succession, the BDC sets the ERASE bit in BDCCSR and requests a flash mass erase. Any other BDC S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 167: Bdc Access Of Internal Resources
Illegal address access, whereby ILLACC is set • Invalid READ_SAME or DUMP_MEM sequence • Invalid READ_Rn command (BDM inactive or CRN incorrect) • Internal resource read with timeout, whereby NORESP is set S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 168 5-10. Thus if address bits [1:0] are both logic “1” the access is realigned so that it does not straddle the 4-byte boundary but accesses data from within the addressed 4-byte field. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 169 Accessed Accessed Accessed DUMP_MEM.32 0x004004 Accessed Accessed Accessed Accessed DUMP_MEM.16 0x004008 Accessed Accessed DUMP_MEM.16 0x00400A Accessed Accessed DUMP_MEM.08 0x00400C Accessed DUMP_MEM.16 0x00400D Accessed Accessed DUMP_MEM.16 0x00400E Accessed Accessed DUMP_MEM.16 0x004010 Accessed Accessed S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 170: Bdc Serial Interface
BDC. The BDC serial interface uses an internal clock source, selected by the CLKSW bit in the BDCCSR register. This clock is referred to as the target clock in the following explanation. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 171 1 from the target system. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 172 Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 173: Serial Interface Hardware Handshake (Ack Pulse) Protocol
ACK PULSE 32 CYCLES SPEED UP PULSE MINIMUM DELAY FROM THE BDC COMMAND BKGD PIN EARLIEST 16th CYCLE OF THE START OF LAST COMMAND BIT NEXT BIT Figure 5-9. Target Acknowledge Pulse (ACK) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 174 BDC DECODES COMMAND THE COMMAND Figure 5-10. Handshake Protocol at Command Level Alternatively, setting the STEAL bit configures the handshake protocol to make an immediate internal access, independent of free bus cycles. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 175: Hardware Handshake Abort Procedure
5.4.4.1”. Figure 5-11 shows a SYNC command being issued after a READ_MEM, which aborts the READ_MEM command. Note that, after the command is aborted a new command is issued by the host. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 176: Hardware Handshake Disabled (Ack Pulse Disabled)
If the ACK pulse protocol is disabled, the host needs to use the worst case delay time at the appropriate places in the protocol. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 177: Single Stepping
STEP1 has actually not finished. When an interrupt occurs the device leaves wait mode, enters active BDM and the PC points to the start of the corresponding interrupt service routine. A further ACK related to stepping over the WAI is not generated. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 178: Serial Communication Timeout
BDCSI clock frequency is expressed by Minimum f = (3/(#DLY cycles -4))f (core clock) (BDCSI clock) For the standard 16 period DLY this yields f >= (1/4)f (core clock) (BDCSI clock) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 179: Introduction
DBG module. Alternatively the DBG module can be configured over a serial interface using SWI routines. 6.1.1 Glossary Table 6-2. Glossary Of Terms Term Definition Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt Program Counter S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 180: Overview
— State transitions forced by an external event • The following types of breakpoints — CPU breakpoint entering active BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI) • Trace control S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 181: Modes Of Operation
EVENT CONTROL MATCH1 COMPARATOR B BREAKPOINT MATCH2 REQUESTS COMPARATOR C MATCH3 COMPARATOR D TRACE CONTROL TRIGGER PROFILE OUTPUT TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 6-1. Debug Module Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 182: External Signal Description
Address Name Bit 7 Bit 0 0x0100 DBGC1 reserved BDMBP BRKCPU reserved EEVE TRIG 0x0101 DBGC2 CDCM ABCM Figure 6-2. Quick Reference to DBG Registers S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 183 DBGAA[23:16] 0x0116 DBGAAM DBGAA[15:8] 0x0117 DBGAAL DBGAA[7:0] 0x0118 DBGAD0 Bit 31 Bit 24 0x0119 DBGAD1 Bit 23 Bit 16 0x011A DBGAD2 Bit 15 Bit 8 Figure 6-2. Quick Reference to DBG Registers S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 184 DBGCA[23:16] 0x0136 DBGCAM DBGCA[15:8] 0x0137 DBGCAL DBGCA[7:0] 0x0138 DBGCD0 Bit 31 Bit 24 0x0139 DBGCD1 Bit 23 Bit 16 0x013A DBGCD2 Bit 15 Bit 8 Figure 6-2. Quick Reference to DBG Registers S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 185: Register Descriptions
DBG module registers that can be written are ARM, and TRIG 6.3.2.1 Debug Control Register 1 (DBGC1) Address: 0x0100 0x0100 reserved BDMBP BRKCPU reserved EEVE TRIG Reset Figure 6-3. Debug Control Register (DBGC1) Read: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 186: Description
External event function disabled External event forces a trace buffer entry if tracing is enabled External event is mapped to the state sequencer, replacing comparator channel 3 External event pin gates trace buffer entries S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 187 Match0 mapped to comparator A match..Match1 mapped to comparator B match. Match0 mapped to comparator A/B inside range..Match1 disabled. Match0 mapped to comparator A/B outside range..Match1 disabled. Reserved 1. Currently defaults to Match0 mapped to inside range: Match1 disabled S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 188 Trace only in address range from $00000 to Comparator D Trace only in address range from Comparator C to $FFFFFF Trace only in range from Comparator C to Comparator D Table 6-10. TRCMOD Trace Mode Bit Encoding TRCMOD Description Normal Loop1 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 189 Profile Enable — This bit, when set, enables the profile function, whereby a subsequent arming of the DBG PROFILE activates profiling. When PROFILE is set, the TRCMOD bits are ignored. 0 Profile function disabled 1 Profile function enabled S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 190 0xEEEE. The POR state is undefined Other resets do not affect the trace buffer contents. 6.3.2.6 Debug Count Register (DBGCNT) Address: 0x0106 Reset — — — — — — — = Unimplemented or Reserved Figure 6-8. Debug Count Register (DBGCNT) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 191 Figure 6-1 and described in Section 6.3.2.12”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 192 These bits select the targeted next state whilst in State2 following a match0. 3–2 Channel 1 State Control. C1SC[1:0] These bits select the targeted next state whilst in State2 following a match1. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 193 These bits select the targeted next state whilst in State3 following a match1. 5–4 Channel 2 State Control. C2SC[1:0] These bits select the targeted next state whilst in State3 following a match2. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 194 0 No trace buffer overflow event 1 Trace buffer overflow event TRIG Flag — Indicates the occurrence of a TRIG event during the debug session. TRIGF 0 No TRIG event 1 TRIG event S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 195 State1 and these bits are forced to SSF[2:0] = 001. See Table 6-24 Table 6-24. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] Current State State0 (disarmed) State1 State2 State3 Final State S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 196 Table 6-26 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if INST is set, because matches based on opcodes reaching the execution stage are data independent. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 197 DBGAA the address bus bits [15:0] to a logic one or logic zero. [15:0] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 198 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Figure 6-17. Debug Comparator A Data Mask Register (DBGADM) Read: Anytime. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 199 Enable Bit — Determines if comparator is enabled COMPE 0 The comparator is not enabled 1 The comparator is enabled 1. If the ABCM field selects range mode comparisons, then DBGACTL bits configure the comparison, DBGBCTL is ignored. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 200 DBGBA the address bus bits [15:0] to a logic one or logic zero. [15:0] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 201 INST is set, because matches based on opcodes reaching the execution stage are data independent. Table 6-34. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment RW not used in comparison RW not used in comparison Write match No match No match S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 202 DBGCA the address bus bits [15:0] to a logic one or logic zero. [15:0] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 203 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Figure 6-23. Debug Comparator C Data Mask Register (DBGCDM) Read: Anytime. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 204 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Enable Bit — Determines if comparator is enabled COMPE 0 The comparator is not enabled 1 The comparator is enabled S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 205 DBGDA the address bus bits [23:16] to a logic one or logic zero. [23:16] 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 206: Functional Description
Comparator Modes The DBG contains four comparators, A, B, C, and D. Each comparator compares the address stored in DBGXAH, DBGXAM, and DBGXAL with the PC (opcode addresses) or selected address bus (data S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 207 Table 6-41. Comparator Address Bus Matches Access Address ADDR[n] ADDR[n+1] ADDR[n+2] ADDR[n+3] 32-bit ADDR[n] Match Match Match Match 16-bit ADDR[n] Match Match No Match No Match 16-bit ADDR[n+1] No Match Match Match No Match S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 208 32-bit DBGxD0 DBGxD1 DBGxD2 DBGxD3 32-bit DBGxD1 DBGxD2 DBGxD3 DBGxD0 32-bit DBGxD2 DBGxD3 DBGxD0 DBGxD1 32-bit DBGxD3 DBGxD0 DBGxD1 DBGxD2 16-bit DBGxD0 DBGxD1 16-bit DBGxD1 DBGxD2 16-bit DBGxD2 DBGxD3 16-bit DBGxD3 DBGxD0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 209 (inside range) or outside the range (outside range). For opcode comparisons only the address of the first opcode byte is compared with the range. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 210: Events
Opcode address matches are data independent thus the RWE and RW bits are ignored. CPU compares are disabled when BDM becomes active. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 211 ARM bit is cleared due to the hardware disarm. Table 6-45. Event Priorities Priority Source Action Highest TB Overflow Immediate force to state 0, generate breakpoint and terminate tracing S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 212: State Sequence Control
If tracing is disabled or End aligned triggering is selected, then when the Final State is reached the state sequencer returns to State0 immediately and the debug module is disarmed. If breakpoints are enabled, a breakpoint request is generated on transitions to State0. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 213: Trace Buffer Operation
Storing with Begin-Alignment, data is not stored in the trace buffer until the Final State is entered. Once the trigger condition is met the DBG module remains armed until 64 lines are stored in the trace buffer. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 214 COF addresses stored include the full address bus of CPU and an information byte, which contains bits to indicate whether the stored address was a source, destination or vector address. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 215 Normal mode profiling with timestamp is possible when tracing from a single source by setting the STAMP bit in DBGTCRL. This results in a different format (see Table 6-48). Table 6-47. Normal and Loop1 Mode Trace Buffer Format without Timestamp 8-Byte Wide Trace Buffer Line Mode S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 216 1 Trace buffer entry initiated by a timestamp overflow Table 6-50. CET Encoding Entry Type Description Non COF opcode address (entry forced by an external event) Vector destination address Source address of COF opcode Destination address of COF opcode S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 217 Table 6-51. Detail Mode Trace Buffer Format without Timestamp 8-Byte Wide Trace Buffer Line Mode CDATA31 CDATA21 CDATA11 CDATA01 CINF1 CADRH1 CADRM1 CADRL1 Detail CDATA32 CDATA22 CDATA12 CDATA02 CINF2 CADRH2 CADRM2 CADRL2 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 218 Bit 2 Bit 1 Bit 0 CINF TSINF TOVF Figure 6-28. Information Bytes CINF and XINF When tracing in Detail Mode, CINF provides information about the type of CPU access being made. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 219 Each trace buffer line is filled from right to left. The final entry on each line is always a base address, used as a reference for the previous entries on the same line. Whilst tracing, a base address is typically stored S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 220 When set, the STAMP bit in DBGTCRL configures the DBG to add a timestamp to trace buffer entries in Normal, Loop1 and Detail trace buffer modes. The timestamp is generated from a 16-bit counter and is stored to the trace buffer line each time a trace buffer entry is made. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 221 Whilst reading, an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0. The S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 222: Code Profiling
The external debugger uses both edges of the clock output to strobe the data on PDO. The first PDOCLK edge is used to sample the first data bit on PDO. Figure 6-30. Profiling Output Interface CLOCK PDOCLK DATA TBUF DEV TOOL S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 223 When the DBG module is disarmed but profiling transmission is ongoing, register write accesses are suppressed. When the DBG module is disarmed but profiling transmission is still ongoing, reading from the DBGTB returns the code 0xEE. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 224 PTIB/PTVB/PTHF format is used. Since the development tool receives the INFO byte first, it can determine in advance the format of data it is about to receive. The S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 225 Line2 indicates that an indirect COF occurred after 8 direct COF entries. The indirect COF address is stored in bytes 7 to 5. All bits to the left of the stop bit are redundant. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 226: Breakpoints
Final State, then TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent comparator match, it has no effect, since tracing has already started. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 227: Application Information
In this way it is possible to analyze the sequence of events emerging from reset. The recommended handling of the internal reset scenario is as follows: S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 228: Breakpoints From Other S12Z Sources
No start bit is provided. The external development tool must detect this first rising edge after arming the DBG. To detect the end of profiling, the DBG ARM bit can be monitored using the BDC. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 229: Introduction
• The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter. • The Internal Reference Clock (IRC1M) provides a 1MHz internal clock. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 230: Features
Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based. • PLL stability is sufficient for LIN communication in slave mode, even if using IRC1M as reference clock The Internal Reference Clock (IRC1M) has the following features: S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 231 — Low-voltage reset (LVR) — COP system watchdog, COP reset on time-out, windowed COP — Loss of oscillation (Oscillator clock monitor fail) — Loss of PLL clock (PLL clock monitor fail) — External pin RESET S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 232: Modes Of Operation
PLL configuration is used for the selected oscillator frequency. — This mode can be entered from default mode PEI by performing the following steps: – Make sure the PLL configuration is valid for the selected oscillator frequency. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 233 Full Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active) depending on the setting of bit CSAD. When bit CSAD is set the ACLK clock source for the S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 234 Additionally the COP can be forced to the maximum time-out period in Active BDM Mode. For details please see also the RSBCK and CR[2:0] bit description field of Table 7-14 Section 7.3.2.10, “S12CPMU_UHV_V5 COP Control Register (CPMUCOP) S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 235: S12Cpmu_Uhv_V5 Block Diagram
Osc. RTI Interrupt RTIE COP time-out COPCLK IRCCLK to Reset Watchdog Generator IRCCLK Real Time OSCCLK RTICLK Interrupt (RTI) OSCCLK CPMUCOP COPOSCSEL0 RTIOSCSEL CPMURTI UPOSC=0 clears Figure 7-1. Block diagram of S12CPMU_UHV_V5 S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 236 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5) Figure 7-2 shows a block diagram of the XOSCLCP. OSCMOD Clock monitor fail Monitor OSCCLK Peak Gain Control Detector VDD=1.8V Quartz Crystals XTAL EXTAL Ceramic Resonators Figure 7-2. XOSCLCP Block Diagram S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 237: Signal Description
VDDA has to be connected externally to VDDX. 7.2.5 VDDX, VSSX — Pad Supply Pins VDDX is the supply domain for the digital Pads. An off-chip decoupling capacitor (10F plus 220 nF(X7R ceramic)) between VDDX and VSSX is required. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 238: Bctl — Base Control Pin For External Pnp
Depending on the VSEL setting either the voltage level generated by the temperature sensor or the VREG bandgap voltage is driven to a special channel input of the ADC Converter. See device level specification for connectivity of ADC special channels. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 239: Memory Map And Registers
0x000A CPMUPLL 0x000B CPMURTI RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 0x000C CPMUCOP WCOP RSBCK WRTMASK RESERVED 0x000D CPMUTEST0 RESERVED 0x000E CPMUTEST1 = Unimplemented or Reserved Figure 7-3. CPMU Register Summary S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 240 IRCTRIML 0x001A CPMUOSC OSCE Reserved 0x001B CPMUPROT PROT RESERVED 0x001C CPMUTEST2 CPMU 0x001D EXTXON INTXON VREGCTL 0x001E CPMUOSC2 OMRE OSCMOD CPMU 0x001F RESERVED1F = Unimplemented or Reserved Figure 7-3. CPMU Register Summary S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 241: Register Descriptions
7.3.2.10, “S12CPMU_UHV_V5 COP Control Register (CPMUCOP) for details.This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 COP reset has not occurred. 1 COP reset has occurred. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 242 The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 243 2MHz range. The bits can still be written but will have no effect on the PLL filter configuration. For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability). S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 244 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5) Table 7-4. Reference Clock Frequency Selection if OSC_LCP is enabled REFCLK Frequency Ranges REFFRQ[1:0] (OSCE=1) 1MHz <= f <= 2MHz 2MHz < f <= 6MHz 6MHz < f <= 12MHz >12MHz S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 245 (increases or decreases) f in order to avoid sudden load changes for the on-chip voltage regulator. 7.3.2.5 S12CPMU_UHV_V5 Interrupt Flags Register (CPMUIFLG) This register provides S12CPMU_UHV_V5 status bits and interrupt flags. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 246 Oscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. Entering Full Stop UPOSC Mode UPOSC is cleared. 0 The oscillator is off or oscillation is not qualified by the PLL. 1 The oscillator is qualified by the PLL. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 247 0 PLL LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. Oscillator Corrupt Interrupt Enable Bit OSCIE 0 Oscillator Corrupt interrupt requests are disabled. 1 Interrupt will be requested whenever OSCIF is set. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 248 (write OMRE = 1 in CPMUOSC2 register). If the oscillator monitor reset feature is disabled (OMRE = 0) and the oscillator clock is used as system clock, the system will stall in case of loss of oscillation. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 249 1 COP continues running during Pseudo Stop Mode if COPOSCSEL=1 Note: If PCE=0 or COPOSCSEL=0 then the COP will go static while Stop Mode is active. The COP counter will not be reset. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 250 UPOSC= 0 clears the COPOSCSEL0 bit. 0 COP clock source is IRCCLK. 1 COP clock source is OSCCLK Table 7-8. COPOSCSEL1, COPOSCSEL0 clock source select description COPOSCSEL1 COPOSCSEL0 COP clock source IRCCLK OSCCLK ACLK S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 251 The modulation frequency is f divided by 16. See Table 7-10 for coding. Table 7-10. FM Amplitude selection FM Amplitude / Variation FM off 1% 2% 4% S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 252 Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to RTR[3:0] provide additional granularity.Table 7-12 Table 7-13 show all possible divide values selectable by the CPMURTI register. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 253 15x2 1110 (15) 16x2 16x2 16x2 16x2 16x2 16x2 16x2 1111 (16) Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 254 1100 (13) 14x10 28x10 70x10 140x10 280x10 700x10 1.4x10 2.8x10 1101 (14) 15x10 30x10 75x10 150x10 300x10 750x10 1.5x10 3x10 1110 (15) 16x10 32x10 80x10 160x10 320x10 800x10 1.6x10 3.2x10 1111 (16) S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 255 2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0. 3. Changing RSBCK bit from “0” to “1”. In Special Mode, any write access to CPMUCOP register restarts the COP time-out period. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 256 4) Operation in Special Mode Table 7-15. COP Watchdog Rates if COPOSCSEL1=0. (default out of reset) COPCLK Cycles to time-out (COPCLK is either IRCCLK or OSCCLK depending on the COPOSCSEL0 bit) COP disabled S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 257 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5) Table 7-16. COP Watchdog Rates if COPOSCSEL1=1. COPCLK Cycles to time-out (COPCLK is ACLK divided by 2) COP disabled S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 258 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V5’s functionality. Module Base + 0x000E Reset = Unimplemented or Reserved Figure 7-15. Reserved Register (CPMUTEST1) Read: Anytime Write: Only in Special Mode S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 259 Module Base + 0x0010 HTDS VSEL HTIE HTIF Reset = Unimplemented or Reserved Figure 7-17. High Temperature Control Register (CPMUHTCTL) Read: Anytime Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 260 1 HTDS bit has changed. NOTE The voltage at the temperature sensor can be computed as follows: (temp) = V - (150 - temp) * dV HT(150) Figure 7-18. Voltage Access Select TEMPSENSE VSEL Channel S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 261 Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by LVIF writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 262 This flag can only be cleared by writing a 1.Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API time-out has not yet occurred. 1 API time-out has occurred. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 263 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5) Figure 7-21. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) API min. period / 2 APIES=0 API period APIES=1 S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 264 ACLK period time. Table 7-21. Trimming Effect of ACLKTR[5:0] ACLKTR[5:0] Decimal ACLK frequency 100000 lowest 100001 increasing ..111111 000000 000001 increasing ..011110 011111 highest S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 265 For APICLK bit clear the first time-out period of the API will show a latency time between two to three f cycles due to synchronous clock ACLK gate release when the API feature gets enabled (APIFE bit set) S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 266 12 * Bus Clock period ..FFFD 131068 * Bus Clock period FFFE 131070 * Bus Clock period FFFF 131072 * Bus Clock period When f is trimmed to 20KHz. ACLK S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 267 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V5’s functionality. Module Base + 0x0016 Reset = Unimplemented or Reserved Figure 7-25. Reserved Register (CPMUTEST3) Read: Anytime Write: Only in Special Mode S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 268 HTTR[3:0] Table 7-26. Trimming Effect of HTTR Temperature Interrupt threshold HTTR[3:0] sensor voltage V temperatures T and T HTIA HTID 0000 lowest highest 0001 increasing decreasing ..1110 1111 highest lowest S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 269 0.15%, i.e. 0.3% is the distance between two trimming values). Figure 7-29 shows the relationship between the trim bits and the resulting IRC1M frequency. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 270 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5) IRC1M frequency (IRCCLK) IRCTRIM[9:6] 1.5MHz ..IRCTRIM[5:0] 1MHz 600KHz IRCTRIM[9:0] $000 $3FF Figure 7-29. IRC1M Frequency Trimming Diagram S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 271 Setting TCTRIM[4:0] at 0x00000 or 0x10000 does not mean that the temperature coefficient will be zero. These two combinations basically switch off the TC compensation module, which results in the nominal TC of the IRC1M. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 272 NOTE Since the IRC1M frequency is not a linear function of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 273 Figure 7-31. S12CPMU_UHV_V5 Oscillator Register (CPMUOSC) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE. Write to this register clears the LOCK and UPOSC status bits. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 274 Pseudo Stop Mode. UPOSC Do not alter this bit from its reset value. It is for Manufacturer use only and can change the Oscillator behavior. Reserved S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 275 (see list of protected registers above): Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit. 0 Protection of clock configuration registers is disabled. 1 Protection of clock configuration registers is enabled. (see list of protected registers above). S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 276 Writing to this register when in Special Mode can alter the S12CPMU_UHV_V5’s functionality. Module Base + 0x001C Reset = Unimplemented or Reserved Figure 7-33. Reserved Register CPMUTEST2 Read: Anytime Write: Only in Special Mode S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 277 Internal voltage regulator Enable Bit for VDDX domain— Should be set to 1 if no external BJT is present on INTXON the PCB, cleared otherwise. 0 VDDX control loop does not use internal power transistor 1 VDDX control loop uses internal power transistor S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 278 If OSCE bit in CPMUOSC register is 1, then the OSCMOD bit can not be changed (writes will have no effect). 0 External oscillator configured for loop controlled mode (reduced amplitude on EXTAL and XTAL)) 1 External oscillator configured for full swing mode (full swing amplitude on EXTAL and XTAL) S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 279: Functional Description
If PLL is selected (PLLSEL=1) f bus NOTE Although it is possible to set the dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 280 In case of loss of reference clock (e.g. IRCCLK) the PLL will not lock or if already locked, then it will unlock. The frequency of the VCOCLK will be very low and will depend on the value of the VCOFRQ[1:0] bits. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 281: Startup From Reset
Bus Clock = Core Clock/2 lock LOCK $18 (default target f =50MHz) SYNDIV $03 (default target f /4 = 12.5MHz) POSTDIV example change reset state startup vector fetch, program execution of POSTDIV cycles STARTUP S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 282: Stop Mode Using Pllclk As Source Of The Bus Clock
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is shown in Figure 7-38. Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going into Full Stop Mode. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 283 Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details). S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 284: External Oscillator
OSCCLK UPOSC flag is set upon successful start of oscillation UPOSC UPOSC select OSCCLK as Core/Bus Clock by writing PLLSEL to zero PLLSEL based on OSCCLK based on PLL Clock Core Clock S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 285: System Clock Configurations
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again. Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 286: Resets
MCU specification for reset vector address. Table 7-34. Reset Summary Reset Source Local Enable Power-On Reset (POR) None Low Voltage Reset (LVR) None External pin RESET None PLL Clock Monitor Reset None S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 287: Description Of Reset Operation
CMFA (see device electrical characteristics for values), the S12CPMU_UHV_V5 generates an Oscillator Clock Monitor Reset. In Full Stop Mode the external oscillator and the oscillator clock monitor are disabled. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 288: Pll Clock Monitor Reset
OSCE UPOSC (clock source) Run (ACLK) Static (ACLK) Run (OSCCLK) Static (IRCCLK) Static (IRCCLK) Static (IRCCLK) Static (OSCCLK) Static (OSCCLK) Static (IRCCLK) Static (IRCCLK) Satic (OSCCLK) Static (IRCCLK) Static (IRCCLK) Static (IRCCLK) S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 289: Power-On Reset (Por)
The LVR assert and deassert levels for the supply voltage VDDX are V and V and are LVRXA LVRXD specified in the device Reference Manual.The LVR circuitry is active in Run- and Wait Mode. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 290: Interrupts
0 by writing a 1 to the LOCKIF bit. 7.6.1.3 Oscillator Status Interrupt When the OSCE bit is 0, then UPOSC stays 0. When OSCE=1 the UPOSC bit is set after the LOCK bit is set. S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 291 The API Trimming bits ACLKTR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. Table 7-21 for the trimming effect of ACLKTR[5:0]. 1. For details please refer to “7.4.6 System Clock Configurations” S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 292: Initialization/Application Information
If the COP is stopped during any Stop Mode it is recommended to service the COP shortly before Stop Mode is entered. 7.7.3 Application Information for PLL and Oscillator Startup The following C-code example shows a recommended way of setting up the system clock system using the PLL and Oscillator: S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 293 /* put your code to loop and wait for the LOCKIF or */ /* poll CPMUIFLG register until both LOCK status is “1” */ /* that is CPMIFLG == 0x18 */ /*....continue to your main code execution here....*/ S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 294 Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5) S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05 Freescale Semiconductor...
Page 295: Introduction
8.1.1 Features The TIM16B8CV3 includes these distinctive features: • Up to 8 channels available. (refer to device specification for exact number) • All channels have same input capture/output compare functionality. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 296: S12Zvhy/S12Zvhl Family Reference Manual Rev. 1.05 Freescale Semiconductor
Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0. 8.1.3 Block Diagrams S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 297 Input capture IOC7 Pulse accumulator Output compare PA input interrupt Maximum possible channels, scalable from 0 to 7. Pulse Accumulator is available only if channel 7 exists. Figure 8-1. TIM16B8CV3 Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 298 Interrupt PACNT Divide by 64 M clock Figure 8-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer IOCn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 8-3. Interrupt Flag Setting S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 299: External Signal Description
8-5. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B8CV3 module and the address offset for each register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 300: Register Descriptions
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0020 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PACTL Figure 8-5. TIM16B8CV3 Register Summary (Sheet 1 of 2) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 301 Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description Input Capture or Output Compare Channel Configuration IOS[7:0] 0 The corresponding implemented channel acts as an input capture. 1 The corresponding implemented channel acts as an output compare. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 302 8.3.2.3 Output Compare 7 Mask Register (OC7M) Module Base + 0x0002 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 Reset Figure 8-8. Output Compare 7 Mask Register (OC7M) Read: Anytime Write: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 303 7 mask register. 8.3.2.5 Timer Count Register (TCNT) Module Base + 0x0004 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 Reset Figure 8-10. Timer Count Register High (TCNTH) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 304 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 305 When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 306 Table 8-9. Compare Result Output Action Action No output compare action on the timer output signal Toggle OCx output line Clear OCx output line to zero Set OCx output line to one S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 307 EDG4B EDG4A Reset Figure 8-16. Timer Control Register 3 (TCTL3) Module Base + 0x000B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A Reset Figure 8-17. Timer Control Register 4 (TCTL4) Read: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 308 Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in C7I:C0I the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 309 Bus Clock / 1 Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 310 TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one. Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 311 All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should take place before low byte otherwise it will give a different result. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 312 CLK[1:0] Pulse Accumulator Overflow Interrupt Enable PAOVI 0 Interrupt inhibited. 1 Interrupt requested if PAOVF is set. Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 313 When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags in the PAFLG register. Timer module or Pulse Accumulator must stay enabled (TEN=1 or PAEN=1) while clearing these bits. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 314 Reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the Bus clock first. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 315 Precision Timer Prescaler Select Register (PTPSR) Module Base + 0x002E PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Reset Figure 8-29. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 316: Functional Description
PTPS3 PTPS2 PTPS1 PTPS0 Factor Functional Description This section provides a complete functional description of the timer TIM16B8CV3 block. Please refer to the detailed timer block diagram in Figure 8-30 as necessary. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 317 DIVIDE-BY-64 PAOVI clock PAOVF PAIF PAOVF PAOVI Maximum possible channels, scalable from 0 to 7. Pulse Accumulator is available only if channel 7 exists. Figure 8-30. Detailed Timer Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 318: Prescaler
7 output compares to reset the timer counter. A channel 7 output compare can reset the timer counter even if the IOC7 pin is being used as the pulse accumulator input. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 319: Pulse Accumulator
Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the mode of operation. The minimum pulse width for the PAI input is greater than two Bus clocks. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 320: Event Counter Mode
Interrupts This section describes interrupts originated by the TIM16B8CV3 block. Table 8-25 lists the interrupts generated by the TIM16B8CV3 to communicate with the MCU. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 321: Channel [7:0] Interrupt (C[7:0]F)
Timer Overflow Interrupt (TOF) This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block only generates the interrupt and does not service it. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 322 Chapter 8 Timer Module (TIM16B8CV3) Block Description S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 323: Introduction
Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies • Programmable clock select logic 9.1.2 Modes of Operation There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 324: Block Diagram
Maximum possible channels, scalable in pairs from PWM0 to PWM7. Figure 9-1. Scalable PWM Block Diagram External Signal Description The scalable PWM module has a selected number of external pins. Refer to device specification for exact number. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 325: Pwm7 - Pwm0 — Pwm Channel 7 - 0
CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 PWMCAE 0x0005 CON67 CON45 CON23 CON01 PSWAI PFRZ PWMCTL = Unimplemented or Reserved Figure 9-2. The scalable PWM Register Summary (Sheet 1 of 4) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 326 Bit 7 Bit 0 PWMCNT5 0x0012 Bit 7 Bit 0 PWMCNT6 0x0013 Bit 7 Bit 0 PWMCNT7 = Unimplemented or Reserved Figure 9-2. The scalable PWM Register Summary (Sheet 2 of 4) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 327 Bit 7 Bit 0 PWMDTY4 0x0021 Bit 7 Bit 0 PWMDTY5 0x0022 Bit 7 Bit 0 PWMDTY6 = Unimplemented or Reserved Figure 9-2. The scalable PWM Register Summary (Sheet 3 of 4) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 328 While in run mode, if all existing PWM channels are disabled (PWMEx–0 = 0), the prescaler counter shuts off for power savings. Module Base + 0x0000 PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 Reset Figure 9-3. PWM Enable Register (PWME) Read: Anytime Write: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 329 PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 330 Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 331 PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 332 CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 Reset Figure 9-7. PWM Center Align Enable Register (PWMCAE) Read: Anytime Write: Anytime NOTE Write these bits only when the corresponding channel is disabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 333 When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. Section 9.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM Function. NOTE Change these bits only when both corresponding channels are disabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 334 1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation. 9.3.2.7 PWM Clock A/B Select Register (PWMCLKAB) Each PWM channel has a choice of four clocks to use as the clock source for that channel as described below. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 335 0 Clock A or SA is the clock source for PWM channel 0, as shown in Table 9-5. 1 Clock B or SB is the clock source for PWM channel 0, as shown in Table 9-5. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 336 Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Module Base + 0x0009 Bit 7 Bit 0 Reset Figure 9-11. PWM Scale B Register (PWMSCLB) Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLB value). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 337 The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 338 The duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to $00) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 339 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Anytime Write: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 340: Functional Description
2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 341 PWM Ch 6 PCLK6 PCLKAB6 Clock to PWM Ch 7 PCLK7 PCLKAB7 Prescale Scale Clock Select Maximum possible channels, scalable in pairs from PWM0 to PWM7. Figure 9-15. PWM Clock Select Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 342 For channels 0, 1, 4, and 5 the clock choices are clock A. For channels 2, 3, 6, and 7 the clock choices are clock B. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 343: Pwm Channel Timers
PWMEx and the clock source. An exception to this is when channels are concatenated. Refer to Section 9.4.2.7, “PWM 16-Bit Functions” for more detail. NOTE The first PWM cycle after enabling the channel can be irregular. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 344 A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 9-16 and described in Section 9.4.2.5, “Left Aligned Outputs” Section 9.4.2.6, “Center Aligned Outputs”. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 345 9-16, as well as performing a load from the double buffer period and duty register to the associated registers, as described in Section 9.4.2.3, “PWM Period and Duty”. The counter counts from 0 to the value in the period register – 1. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 346 PWMDTYx = 1 PWMx Frequency = 10 MHz/4 = 2.5 MHz PWMx Period = 400 ns PWMx Duty Cycle = 3/4 *100% = 75% The output waveform generated is shown in Figure 9-18. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 347 PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx PWMDTYx PWMPERx PWMPERx Period = PWMPERx*2 Figure 9-19. PWM Center Aligned Output Waveform S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 348 When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel, as shown in Figure 9-21. Similarly, when channels 4 and 5 are concatenated, channel 4 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 349 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order 8-bit channel as also shown in Figure 9-21. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 350 Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 351: Resets
• The 8-bit up/down counter is configured as an up counter out of reset. • All the channels are disabled and all the counters do not count. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 352: Interrupts
For channels 0, 1, 4, and 5 the clock choices are clock A. • For channels 2, 3, 6, and 7 the clock choices are clock B. Interrupts The PWM module has no interrupt. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 353: Introduction
The ADCFLWCTL register can be controlled via internal interface only or via data bus only or by both depending on the register access configuration bits ACC_CFG[1:0]. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 354 (see device reference manual for more details). DISABLE S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 355: Key Features
Conversion Command (CSL) loading possible from System RAM or NVM • Single conversion flow control register with software selectable access path • Two conversion flow control modes optimized to different application use cases S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 356: Modes Of Operation
— The RVL buffer select (RVL_SEL) is not changed if a CSL is in process at MCU Stop Mode request. Hence the same buffer will be used after exit from Stop Mode that was used when the Stop Mode request occurred. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 357 — The RVL buffer select (RVL_SEL) is not changed if a CSL is in process at MCU Wait Mode request. Hence the same RVL buffer will be used after exit from Wait Mode that was used when Wait Mode request occurred. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 358 Freeze Mode is entered. After exit from MCU Freeze Mode with previously frozen conversion sequence the ADC continues the conversion with the next conversion command and all ADC interrupt flags are unchanged during MCU Freeze Mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 359: Block Diagram
Register (SAR) VRL_0 ... Alternative and C-DAC ... Result ... List VDDA ... (RAM) Result 63 VSSA Final ..Buffer ext. Buffer Comparator Channel Sample & Hold ADC12B_LBA Figure 10-2. ADC12B_LBA Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 360: Signal Description
Please refer to the device reference manual for availability and connectivity of these pins. 10.3.1.3 VDDA, VSSA These pins are the power supplies for the analog circuitry of the ADC12B_LBA block. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 361: Memory Map And Register Definition
EOL_IE 0x000B ADCCONIE_1 CON_IE[7:1] 0x000C ADCCONIF_0 CON_IF[15:8] 0x000D ADCCONIF_1 CON_IF[7:1] EOL_IF R CSL_IMD RVL_IMD 0x000E ADCIMDRI_0 RIDX_IMD[5:0] 0x000F ADCIMDRI_1 = Unimplemented or Reserved Figure 10-3. ADC12B_LBA Register Summary (Sheet 1 of 3) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 362: Address Name Bit
ADCRIDX RES_PTR[19:16] 0x0021 ADCRBP_0 0x0022 ADCRBP_1 RES_PTR[15:8] 0x0023 ADCRBP_2 RES_PTR[7:2] CMDRES_OFF0[6:0] 0x0024 ADCCROFF0 0x0025 ADCCROFF1 CMDRES_OFF1[6:0] 0x0026 Reserved Reserved = Unimplemented or Reserved Figure 10-3. ADC12B_LBA Register Summary (Sheet 2 of 3) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 363 Name Bit 7 Bit 0 0x0027 Reserved Reserved 0x0028 Reserved Reserved R Reserved Reserved 0x0029 Reserved 0x002A- Reserved 0x003F = Unimplemented or Reserved Figure 10-3. ADC12B_LBA Register Summary (Sheet 3 of 3) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 364: Radc_En
ADC freezes the conversion at next conversion boundary at Freeze Mode entry. Wait Mode Configuration — This bit influences conversion flow during Wait Mode. SWAI ADC continues conversion in Wait Mode. ADC halts the conversion at next conversion boundary at Wait Mode entry. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 365 Each conversion flow control bit (SEQA, RSTA, TRIG, LDOK) must be controlled by software or internal interface according to the requirements described in Section 10.5.3.2.4, “The two conversion flow control Mode Configurations and overview summary in Table 10-10. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 366 ADC conversion flow control mode “Trigger Mode” and “Restart Mode” (anytime during application runtime). No automatic Restart Event after exit from MCU Stop Mode. 1 Automatic Restart Event occurs after exit from MCU Stop Mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 367: Rcsl_Sel
Sequence Abort Event after exit from MCU Wait Mode (see also the Note in Section 10.2.1.2, “MCU Operating Modes). 0 ADC not in idle state. 1 ADC is in idle state. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 368 ADC Clock Prescaler — These 7bits are the binary prescaler value PRS. The ADC conversion clock frequency PRS[6:0] is calculated as follows: f BUS ----------------------------------- -   Refer to Device Specification for allowed frequency range of f ATDCLK S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 369 ADC Resolution 8-bit data Reserved 10-bit data Reserved 12-bit data Reserved 1. Reserved settings cause a severe error at ADC conversion start whereby the CMD_EIF flag is set and ADC ceases operation S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 370 Bus Clock cycles plus an uncertainty of a few Bus Clock cycles. For more details regarding the sample phase please refer to Section 10.5.2.2, “Sample and Hold Machine with Sample Buffer Amplifier. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 371 This bit can be controlled via the internal interface Signal “Trigger” if access control is configured accordingly via ACC_CFG[1:0]. After being set an additional request via internal interface Signal “Trigger“ causes the flag TRIG_EIF to be set. 0 No conversion sequence trigger. 1 Trigger to start conversion sequence. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 372 The LDOK_EIF error flag is also not set in “Restart Mode” if the first Restart Event occurs after: - ADC got enabled - Exit from Stop Mode - ADC Soft-Reset 0 Load of alternative list done. 1 Load alternative list. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 373 Section 10.5.3.2.4, “The two conversion flow control Mode Configurations, Section 10.5.3.2.5, “The four ADC conversion flow control bits Section 10.5.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 374: Eol_Eie
1 Restart Request error interrupt enabled. Load OK Error Interrupt Enable Bit — This bit enables the Load OK error interrupt. LDOK_EIE 0 Load OK error interrupt disabled. 1 Load OK error interrupt enabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 375: Seqad_Ie Conif_Oie
ADCCONIF Register Flags Overrun Interrupt Enable — This bit enables the flag which indicates if an overrun CONIF_OIE situation occurred for one of the CON_IF[15:1] flags or for the EOL_IF flag. 0 No ADCCONIF Register Flag overrun occurred. 1 ADCCONIF Register Flag overrun occurred. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 376: Cmd_Eif
CSL. The ADC ceases operation if this error flag is set (issue of type severe). 0 No “End Of List” error. 1 “End Of List” command type missing in current executed CSL. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 377 - ADC Soft-Reset - ADC used in CSL single buffer mode The ADC continues operation if this error flag is set. 0 No Load OK error situation occurred. 1 Load OK error situation occurred. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 378 The overrun is detected if any of the conversion interrupt flags (CON_IF[15:1]) is set while the first conversion result of a CSL is stored (result of first conversion from top of CSL is stored). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 379: Eol_Ie
1 ADC conversion interrupt enabled. End Of List Interrupt Enable Bit — This bit enables the end of conversion sequence list interrupt. EOL_IE 0 End of list interrupt disabled. 1 End of list interrupt enabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 380: Eol_If
(see also Section 10.8.6, “RVL swapping in RVL double buffer mode and related registers ADCIMDRI and ADCEOLRI. NOTE Overrun situation of a flag CON_IF[15:1] and EOL_IF are indicated by flag CONIF_OIF. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 381 The register ADCIMDRI is updated and simultaneously a conversion interrupt flag CON_IF[15:1] occurs when the corresponding conversion command (conversion command with INTFLG_SEL[3:0] set) has been processed and related data has been stored to RAM. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 382 NOTE The conversion interrupt EOL_IF occurs and simultaneously the register ADCEOLRI is updated when the “End Of List” conversion command type has been processed and related data has been stored to RAM. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 383 Continue Conversion) End Of List (Wrap to top of CSL and: - In “Restart Mode” wait for Restart Event followed by a Trigger - In “Trigger Mode” wait for Trigger or Restart Event) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 384 Table 10-21. Conversion Interrupt Flag Select CON_IF[15:1] INTFLG_SEL[3] INTFLG_SEL[2] INTFLG_SEL[1] INTFLG_SEL[0] Comment 0x0000 No flag set 0x0001 0x0002 0x0004 0x0008 Only one flag can 0x0010 be set ..(one hot coding) 0x0800 0x1000 0x2000 0x4000 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 385 Table 10-23. Analog Input Channel Select CH_SEL[5] CH_SEL[4] CH_SEL[3] CH_SEL[2] CH_SEL[1] CH_SEL[0] Analog Input Channel VRL_0/1 VRH_0/1 (VRH_0/1 + VRL_0/1) / 2 Reserved Reserved Reserved Reserved S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 386 Table 10-23 is the maximum number of implemented analog input channels on the device. Please refer to the device overview of the reference manual for details regarding number of analog input channels. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 387 If bit SMOD_ACC is set modifying this register must be done carefully - only when no conversion and conversion sequence is ongoing. Table 10-25. Sample Time Select Sample Time SMP[4] SMP[3] SMP[2] SMP[1] SMP[0] in Number of ADC Clock Cycles S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 388 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) Table 10-25. Sample Time Select Sample Time SMP[4] SMP[3] SMP[2] SMP[1] SMP[0] in Number of ADC Clock Cycles Reserved Reserved Reserved Reserved S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 389 Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1) 10.4.2.18 ADC Command Register 3 (ADCCMD_3) Module Base + 0x0017 Reserved Reserved Reserved Reset = Unimplemented or Reserved Figure 10-21. ADC Command Register 3 (ADCCMD_3) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 390 CSL start addresses in the memory map. These bits do not represent absolute addresses [5:0] instead it is a sample index (object size 32bit). See also Section 10.5.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) for more details. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 391 RAM or NVM of the memory map. They are used to calculate the final address from which the conversion commands will be loaded depending on which list is active. For more details see Section 10.5.3.2.2, “Introduction of the two Command Sequence Lists (CSLs). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 392 RVL start addresses in the memory map. These bits do not represent absolute addresses instead it is a sample index (object size 16bit). See also Section 10.5.3.2.3, “Introduction of the two Result Value Lists (RVLs) for more details. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 393 RAM of the memory map to which conversion results will be stored to at the end of a conversion. These bits can only be written if bit ADC_EN is clear. See also Section 10.5.3.2.3, “Introduction of the two Result Value Lists (RVLs). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 394 (object size 16bit for RVL, object size 32bit for CSL). See also Section 10.5.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) Section 10.5.3.2.3, “Introduction of the two Result Value Lists (RVLs) for more details. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 395 RVL, object size 32bit for CSL).,These bits can only be modified if bit ADC_EN is clear. See also Section 10.5.3.2.2, “Introduction of the two Command Sequence Lists (CSLs) Section 10.5.3.2.3, “Introduction of the two Result Value Lists (RVLs) for more details. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 396: Functional Description
(Resolution Dependent Length: SRES[2:0]) Sample CAP hold phase "Buffer" "Final" Sample Time Sample Time (2 cycles) (N - 2 cycles) ADC_CLK Figure 10-28. Sampling and Conversion Timing Example (8-bit Resolution, 4 Cycle Sampling) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 397: Digital Sub-Block
(bits CSL_BMOD, RVL_BMOD). The 32-bit wide conversion command is double buffered and the currently active command is visible in the ADC register map at ADCCMD register space. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 398 Command_11 normal conversion to proceed Sequence_3 Command_12 normal conversion Wait for RSTA or LDOK+RSTA Command_13 End Of List Figure 10-29. Example CSL with sequences and an “End Of List” command type identifier S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 399 Command_8 normal conversion Command_9 normal conversion Command_10 normal conversion Command_11 normal conversion Command_12 normal conversion Command_13 End Of List, wrap to top, continue Figure 10-30. Example CSL for continues conversion S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 400 RAM or NVM end address Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index Figure 10-31. Command Sequence List Schema in Double Buffer Mode S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 401 CSL double buffered mode. When the ADC is enabled, the command address registers (ADCCBP, ADCCROFF_0/2, ADCCIDX) are read only and register ADCCIDX is under control of the ADC. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 402 RAM end address Note: Address register names in () are not absolute addresses instead they are a sample offset or sample index Figure 10-33. Result Value List Schema in Double Buffer Mode S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 403 Table 10-32. Conversion Result Justification Overview Conversion Resolution Left Justified Result Right Justified Result (SRES[1:0]) (DJM = 1’b0) (DJM = 1’b1) 8 bit {Result[7:0],8’b00000000} {8’b00000000,Result[7:0]} 10 bit {Result[9:0],6’b000000} {6’b000000,Result[9:0]} 12 bit {Result[11:0],4’b0000} {4’b0000,Result[11:0]} S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 404 — When is the event finished — Mandatory requirements to executed the event A summary of all event combinations is provided by Table 10-10. • Trigger Event Internal Interface Signal: Trigger Corresponding Bit Name: TRIG S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 405 * The current CSL has been aborted or is about to be aborted due to a Sequence Abort Request. – Requested by: - Positive edge of internal interface signal Restart - Write Access via data bus to set control bit RSTA S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 406 Bit LDOK can only be cleared if it was set as described before and both bits (LDOK, RSTA) are cleared when the first conversion command from top of active Sequence Command List is loaded – Mandatory Requirement: No ongoing conversion or conversion sequence Details if using the internal interface: S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 407 * A Sequence Abort request is about to be executed or has been executed. In case bit SEQA is set automatically the Restart error flag RSTA_EIF is set to indicate an unexpected Restart Request. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 408 Sequence Abort Request Overrun: If a Sequence Abort Request occurs whilst bit SEQA is already set, this is defined as a Sequence Abort Request Overrun situation and the overrun request is ignored. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 409 Trigger Event to continue. • If the last executed conversion command was of type “Normal Conversion” the ADC continues command execution in the order of the current CSL (continues conversion). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 410: Resets
The ADC provides one sequence abort done interrupt associated with the sequence abort request for conversion flow control. Hence, there is only one dedicated interrupt flag and interrupt enable bit for conversion sequence abort and it occurs when the sequence abort is done. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 411: Adc Error And Conversion Flow Control Issue Interrupt
In order to make the ADC operational again an ADC Soft-Reset must be issued. Remaining error interrupt flags cause an error interrupt if enabled, but ADC continues operation. The related interrupt flags are: • RSTAR_EIF • LDOK_EIF • CONIF_OIF S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 412: Use Cases And Application Information
The last entirely filled RVL (an RVL where the corresponding CSL has been executed including the “End Of List “ command type) is shown by register ADCEOLRI. The CSL is used in single buffer mode and bit CSL_SEL is forced to 1’b0. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 413: List Usage — Csl Double Buffer Mode And Rvl Double Buffer Mode
Command Sequence List is reached, if bits LDOK and RSTA are set, the commands list is swapped. CSL_0 RVL_0 RVL_1 CSL_1 (unused) Figure 10-38. CSL Double Buffer Mode — RVL Single Buffer Mode Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 414: List Usage — Csl Double Buffer Mode And Rvl Double Buffer Mode
Hence application software can pick up conversion results, or groups of results, or an entire result list driven fully by interrupts. A use case example diagram is shown in Figure 10-40. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 415 One of the CON_IF interrupt flags occurs Delay can vary depending on the DMA performance, and ADC configuration (conversion delay flow using the Trigger to proceed through the CSL) Figure 10-40. RVL Swapping — Use Case Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 416: Conversion Flow Control Application Information
After the Restart Event is finished (bit RSTA is cleared), the ADC accepts a new Trigger Event (bit TRIG can be set) and begins conversion from the top of the currently active CSL. In conversion flow control S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 417 If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 418: Continuous Conversion
AN3 AN1 AN4 IN5 AN3 AN1 AN4 IN5 AN3 AN1 AN3 AN1 AN4 Stop Mode entry Abort Active CSL_0 Active Idle Idle Figure 10-41. Conversion Flow Control Diagram — Continuous Conversion (with Stop Mode) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 419: Triggered Conversion — Single Csl
If bit AUT_RSTA is set before Low Power Mode is entered, the conversion continues automatically as soon as a low power mode (Stop Mode or Wait Mode with bit SWAI set) is exited. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 420: Fully Timing Controlled Conversion
Fully Timing Controlled Conversion) can be used with CSL single buffer mode or with CSL double buffer mode. If using CSL double buffer mode, CSL swapping is performed by issuing a Restart Event with bit LDOK set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 421: Introduction
EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified application software. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 422: Glossary
Receive/ Transmit Engine TXCAN Transmit Interrupt Req. Message Receive Interrupt Req. Control Filtering Errors Interrupt Req. Status Buffering Wake-Up Interrupt Req. Configuration Registers Wake-Up Low Pass Filter Figure 11-1. MSCAN Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 423: Features
For a description of the specific MSCAN modes and the module operation related to the system operating modes refer to Section 11.4.4, “Modes of Operation”. 1. Depending on the actual bit timing and the clock jitter of the PLL. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 424: External Signal Description
CAN bus and has current protection against defective CAN or defective stations. CAN node 2 CAN node n CAN node 1 CAN Controller (MSCAN) TXCAN RXCAN Transceiver CANH CANL CAN Bus Figure 11-2. CAN System S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 425: S12Zvhy/S12Zvhl Family Reference Manual Rev. 1.05 Freescale Semiconductor
MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The detailed register descriptions follow in the order they appear in the register map. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 426 ABTRQ2 ABTRQ1 ABTRQ0 CANTARQ 0x0009 ABTAK2 ABTAK1 ABTAK0 CANTAAK 0x000A CANTBSEL 0x000B IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 CANIDAC 0x000C Reserved 0x000D BOHOLD CANMISC = Unimplemented or Reserved Figure 11-3. MSCAN Register Summary S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 427: Register Descriptions
Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 428 It is set and cleared by the MSCAN. 0 MSCAN is not synchronized to the CAN bus 1 MSCAN is synchronized to the CAN bus S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 429 CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode. 7. Not including WUPE, INITRQ, and SLPRQ. 8. TSTAT1 and TSTAT0 are not affected by initialization mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 430 Bus-Off Recovery Mode — This bit configures the bus-off state recovery mode of the MSCAN. Refer to BORM Section 11.5.2, “Bus-Off Recovery,” for details. 0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification) 1 Bus-off recovery upon user request S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 431 Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing BRP[5:0] (see Table 11-6). Table 11-5. Synchronization Jump Width SJW1 SJW0 Synchronization Jump Width 1 Tq clock cycle S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 432 Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG1[3:0] of the sample point (see Figure 11-44). Time segment 1 (TSEG1) values are programmable as shown in Table 11-9. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 433 A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the CANRIER register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 434 96  receive error counter 128 01 RxWRN: 128  receive error counter 10 RxERR: 11 Bus-off : 256transmit error counter 1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 435 The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 436 RXSTAT[1:0] flags define an additional bus-off state for the receiver (see Section 11.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). 11.3.2.7 MSCAN Transmitter Flag Register (CANTFLG) The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 437 This register contains the interrupt enable bits for the transmit buffer empty interrupt flags. Module Base + 0x0007 Access: User read/write TXEIE2 TXEIE1 TXEIE0 Reset: = Unimplemented Figure 11-11. MSCAN Transmitter Interrupt Enable Register (CANTIER) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 438 (CANTAAK)”) are set and a transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE flag is set. 0 No abort request 1 Abort request pending S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 439 Figure 11-14. MSCAN Transmit Buffer Selection Register (CANTBSEL) 1. Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 440 Reset: = Unimplemented Figure 11-15. MSCAN Identifier Acceptance Control Register (CANIDAC) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 441 FIFO the indicators are updated as well. 11.3.2.13 MSCAN Reserved Register This register is reserved for factory testing of the MSCAN module and is not available in normal system operating modes. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 442 0 Module is not bus-off or recovery has been requested by user in bus-off state 1 Module is bus-off and holds this state until user request 11.3.2.15 MSCAN Receive Error Counter (CANRXERR) This register reflects the status of the MSCAN receive error counter. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 443 Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 444 Module Base + 0x0018 to Module Base + 0x001B Access: User read/write Reset Figure 11-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 445 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit Module Base + 0x001C to Module Base + 0x001F Access: User read/write Reset Figure 11-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 446: Programmer's Model Of Message Storage
TIME bit is set (see Section 11.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp register is written by the MSCAN. The CPU can only read these registers. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 447 All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation All reserved or unused bits of the receive and transmit buffers always read ‘x’. 1. Exception: The transmit buffer priority registers are 0 out of reset. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 448 ID15 IDR1 0x00X2 ID14 ID13 ID12 ID11 ID10 IDR2 0x00X3 IDR3 0x00X4 DSR0 0x00X5 DSR1 0x00X6 DSR2 0x00X7 DSR3 0x00X8 DSR4 0x00X9 DSR5 0x00XA DSR6 0x00XB DSR7 0x00XC DLC3 DLC2 DLC1 DLC0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 449 The identifier registers for an extended format identifier consist of a total of 32 bits: ID[28:0], SRR, IDE, and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0], RTR, and IDE. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 450 Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the ID[17:15] most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 451 In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 452 CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 453 Module Base + 0x00X4 to Module Base + 0x00XB Reset: Figure 11-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping Table 11-32. DSR0–DSR7 Register Field Descriptions Field Description Data bits 7-0 DB[7:0] S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 454 MSCAN and is defined to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms: • All transmission buffers with a cleared TXEx flag participate in the prioritization immediately before the SOF (start of frame) is sent. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 455 Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers: Anytime when RXF is set. Write: Unimplemented S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 456 Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers: Anytime when RXF is set. Write: Unimplemented S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 457: Functional Description
Message Storage CAN Receive / Transmit Engine Memory Mapped I/O MSCAN CPU bus Receiver TXE0 PRIO TXE1 CPU bus MSCAN PRIO TXE2 Transmitter PRIO Figure 11-39. User Model for Message Buffer Organization S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 458 (CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see Section 11.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme makes the handler S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 459 MSCAN shifts the content of RxBG into the receiver FIFO, sets the RXF flag, and 1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 460: Identifier Acceptance Filter
Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters. 1. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 461 IDR3 CAN 2.0A/B ID10 IDR0 IDR1 ID10 IDR2 ID10 IDR3 Standard Identifier CANIDMR0 CANIDMR1 CANIDMR2 CANIDMR3 CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3 ID Accepted (Filter 0 Hit) Figure 11-40. 32-bit Maskable Identifier Acceptance Filter S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 462 IDR1 ID10 IDR2 ID10 IDR3 Standard Identifier CANIDMR0 CANIDMR1 CANIDAR0 CANIDAR1 ID Accepted (Filter 0 Hit) CANIDMR2 CANIDMR3 CANIDAR2 CANIDAR3 ID Accepted (Filter 1 Hit) Figure 11-41. 16-bit Maskable Identifier Acceptance Filters S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 463 ID Accepted (Filter 0 Hit) CIDMR1 CIDAR1 ID Accepted (Filter 1 Hit) CIDMR2 CIDAR2 ID Accepted (Filter 2 Hit) CIDMR3 CIDAR3 ID Accepted (Filter 3 Hit) Figure 11-42. 8-bit Maskable Identifier Acceptance Filters S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 464 If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 465 (PROP_SEG + PHASE_SEG1) (PHASE_SEG2) 4 ... 16 2 ... 8 8 ... 25 Time Quanta = 1 Bit Time Transmit Point Sample Point (single or triple sampling) Figure 11-44. Segments within the Bit Time S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 466: Modes Of Operation
0 .. 3 11.4.4 Modes of Operation 11.4.4.1 Normal System Operating Modes The MSCAN module behaves as described within this specification in all normal system operating modes. Write restrictions exist for some registers. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 467 CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message filters. Section 11.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a detailed description of the initialization mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 468: Low-Power Options
Table 11-37 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 469 This is a non-power-saving mode. Enabling the MSCAN puts the module from disabled mode into normal mode. In this mode the module can either be in initialization mode or out of initialization mode. See Section 11.4.4.5, “MSCAN Initialization Mode”. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 470 RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes place while in sleep mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 471 In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some fixed delay before the module enters normal mode again. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 472: Reset Initialization
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx flag of the empty message buffer is set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 473 For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 474: Initialization/Application Information
128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored • BOHOLD in MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 475: Introduction
This block guide provides an overview of the serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs. 12.1.1 Glossary IR: InfraRed IrDA: Infrared Design Associate IRQ: Interrupt Request S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 476: Features
— Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error — Receive wakeup on active edge — Transmit collision detect supporting LIN — Break Detect supporting LIN S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 477: Modes Of Operation
RXEDG BERR Data Format Control Transmit TDRE Interrupt Transmit Transmit Control 1/16 Generation Baud Rate Generator Infrared Data Out TXD Transmit Shift Register Encoder SCI Data Register Figure 12-1. SCI Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 478: External Signal Description
12-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 479: Register Descriptions
1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved Figure 12-2. SCI Register Summary S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 480 Note: . User should write SCIBD by word access. The updated SCIBD may take effect until next RT clock start, write SCIBDH or SCIBDL separately may cause baud generator load wrong data at that time,if second write later then RT clock. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 481 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit 1 Idle character bit count begins after stop bit S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 482 0 Even parity 1 Odd parity Table 12-4. Loop Functions LOOPS RSRC Function Normal operation Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 483 If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it. 0 No break signal was received 1 A break signal was received S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 484 1 BERRIF interrupt requests enabled Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt BKDIE requests. 0 BKDIF interrupt requests disabled 1 BKDIF interrupt requests enabled S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 485 Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 12-19) Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 12-19) Reserved S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 486 BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 487 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 488 (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 489 Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 490 If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 491 Chapter 12 Serial Communication Interface (S12SCIV6) When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 492: Functional Description
BKDIF Shift Register Break Detect BKDIE SCI Data BKDFE Register LIN Transmit BERRIF Collision SCTXD Detect BERRIE R16XCLK BERRM[1:0] Infrared Transmit Ir_TXD Encoder R32XCLK TNP[1:0] IREN Figure 12-14. Detailed SCI Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 493: Infrared Interface Submodule
LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 494: Data Format
(SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits. Table 12-15. Example of 9-Bit Data Formats Start Data Address Parity Stop Bits Bits Bits S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 495: Baud Rate Generation
76,804.9 4800.3 4,800 .006 10417 38,398.8 2399.9 2,400 .003 20833 19,200.3 1200.02 1,200 41667 9599.9 600.0 65535 6103.6 381.5 1. 16x faster then baud rate 2. divide 1/16 form transmit baud generator S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 496: Transmitter
TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 497 If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 498 Does not clear the SCI data registers (SCIDRH/L) • May set noise flag NF, or receiver active flag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 499 TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 500 If the bit error detect feature is disabled, the bit error interrupt flag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt flag may be set incorrectly. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 501: Receiver
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 502 Table 12-17. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 503 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 12-19 summarizes the results of the stop bit samples. Table 12-19. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 504 RT8, RT9, and RT10 are within the bit time and data recovery is successful. Perceived Start Bit Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 12-23. Start Bit Search Example 2 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 505 Perceived and Actual Start Bit Samples RT Clock RT Clock Count Reset RT Clock Figure 12-25. Start Bit Search Example 4 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 506 FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 507 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19% S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 508 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 509: Single-Wire Operation
Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 510: Loop Operation
NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same. 12.5 Initialization/Application Information 12.5.1 Reset Initialization Section 12.3.2, “Register Descriptions”. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 511: Modes Of Operation
Active high level. The RDRF interrupt indicates that received data is available in the SCI data register. SCISR1[3] Active high level. This interrupt indicates that an overrun condition has occurred. IDLE SCISR1[4] ILIE Active high level. Indicates that receiver input has become idle. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 512 Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened. BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 513 Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 514: Recovery From Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode. 12.5.5 Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 515: Introduction
Double-buffered data register • Serial clock with programmable polarity and phase • Control of SPI operation during wait mode 13.1.3 Modes of Operation The SPI functions in three modes: run, wait, and stop. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 516: Block Diagram
Figure 13-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 517: External Signal Description
MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 518: Ss — Slave Select Pin
SPC0 SPICR2 0x0002 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIBR 0x0003 SPIF SPTEF MODF SPISR 0x0004 SPIDRH 0x0005 SPIDRL 0x0006 Reserved 0x0007 Reserved = Unimplemented or Reserved Figure 13-2. SPI Register Summary S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 519: Register Descriptions
SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 520 Module Base +0x0001 XFRW MODFEN BIDIROE SPISWAI SPC0 Reset = Unimplemented or Reserved Figure 13-4. SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserved bits have no effect S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 521 Master In Master Out Bidirectional MISO not used by SPI Master In Master I/O Slave Mode of Operation Normal Slave Out Slave In Bidirectional Slave In MOSI not used by SPI Slave I/O S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 522 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor 12.5 Mbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s 781.25 kbit/s 390.63 kbit/s 195.31 kbit/s 97.66 kbit/s 6.25 Mbit/s 3.125 Mbit/s 1.5625 Mbit/s 781.25 kbit/s S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 523 1280 19.53 kbit/s 2.08333 Mbit/s 1.04167 Mbit/s 520.83 kbit/s 260.42 kbit/s 130.21 kbit/s 65.10 kbit/s 32.55 kbit/s 1536 16.28 kbit/s 1.78571 Mbit/s 892.86 kbit/s 446.43 kbit/s 223.21 kbit/s 111.61 kbit/s 55.80 kbit/s S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 524 (SPICR2)”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 525 2. Data in SPIDRH is undefined in this case. 3. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF == 1. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 526 If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 13-10). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 527: Functional Description
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 528: Master Mode
If the SS input becomes low this indicates a mode fault error where another master tries to 1. n depends on the selected transfer width, please refer to Section 13.3.2.2, “SPI Control Register 2 (SPICR2) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 529: Slave Mode
SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 530: Transmission Formats
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. 1. n depends on the selected transfer width, please refer to Section 13.3.2.2, “SPI Control Register 2 (SPICR2) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 531 SPI. 1. n depends on the selected transfer width, please refer to Section 13.3.2.2, “SPI Control Register 2 (SPICR2) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 532 , and t are guaranteed for the master mode and required for the slave mode. Figure 13-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 533 A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. 1. n depends on the selected transfer width, please refer to Section 13.3.2.2, “SPI Control Register 2 (SPICR2) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 534 = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 13-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 535: Spi Baud Rate Generation
(SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 13-3. (SPR + 1) BaudRateDivisor = (SPPR + 1)  2 Eqn. 13-3 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 536: Special Features
The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 537: Error Conditions
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 538: Low Power Mode Options
SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 539 The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 13.3.2.4, “SPI Status Register (SPISR)”. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 540 SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 13.3.2.4, “SPI Status Register (SPISR)”. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 541: Introduction
Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 542 Chapter 14 Inter-Integrated Circuit (IICV3) Block Description • Acknowledge bit generation/detection • Bus busy detection • General Call Address detection • Compliant to ten-bit address S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 543: Modes Of Operation
The block diagram of the IIC module is shown in Figure 14-1. Start Stop Registers Arbitration Control Interrupt In/Out Data Clock Shift Control bus_clock Register Address Compare Figure 14-1. IIC Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 544: External Signal Description
IBEN IBIE MS/SL Tx/Rx TXAK IBSWAI IBCR RSTA 0x0003 IAAS RXAK IBAL IBIF IBSR 0x0004 IBDR 0x0005 GCEN ADTYPE ADR10 ADR9 ADR8 IBCR2 = Unimplemented or Reserved Figure 14-2. IIC Register Summary S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 545 — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown Table 14-4. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 546 SCL to SDA changing, the SDA hold time. IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 14-6. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 547 SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap] Table 14-7. IIC Divider and Hold Values (Sheet 1 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) MUL=1 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 548 Table 14-7. IIC Divider and Hold Values (Sheet 2 of 6) IBC[7:0] SCL Divider SDA Hold SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 20/22 22/24 24/26 26/28 28/30 30/32 34/36 40/42 28/32 32/36 36/40 40/44 44/48 48/52 56/60 68/72 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 549 SCL Hold SCL Hold (hex) (clocks) (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MUL=2 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 550 1532 1538 3840 1916 1922 2560 1276 1282 3072 1532 1538 3584 1788 1794 4096 2044 2050 4608 2300 2306 5120 2556 2562 6144 1026 3068 3074 7680 1026 3836 3842 MUL=4 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 551 (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1016 1028 2304 1144 1156 2560 1272 1284 3072 1528 1540 3840 1912 1924 2560 1272 1284 3072 1528 1540 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 552 14.3.1.3 IIC Control Register (IBCR) Module Base + 0x0002 IBEN IBIE MS/SL Tx/Rx TXAK IBSWAI RSTA Reset = Unimplemented or Reserved Figure 14-6. IIC Bus Control Register (IBCR) Read and write anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 553 IIC will be stopped and any transmission currently in progress will halt.If the CPU were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 554 5. A stop condition is detected when the master did not request it. This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 555 In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the required R/W bit (in position D0). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 556: Functional Description
Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 14-10. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 557 (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. START Condition STOP Condition Figure 14-11. Start and Stop Conditions S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 558 This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 14-10). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 559 SCL line low again. Start Counting High Period WAIT SCL1 SCL2 Internal Counter Reset Figure 14-12. IIC-Bus Clock Synchronization S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 560 14-15, the first two bytes are the similar to Figure 14-14. After the repeated START(Sr),the first slave address is transmitted again, but the R/W is 1, meaning that the slave is acted as a transmitter. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 561: Operation In Run Mode
Section 14.3, “Memory Map and Register Definition,” which details the registers and their bit-fields. 14.6 Interrupts IICV3 uses only one interrupt vector. Table 14-11. Interrupt Summary Interrupt Offset Vector Priority Source Description S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 562: Application Information
The bus free time (i.e., the time between a STOP condition and the following START condition) is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 563 A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 564: S12Zvhy/S12Zvhl Family Reference Manual Rev. 1.05 Freescale Semiconductor
Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 565 When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 566 Write Data To IBDR Read Data Dummy Read Generate Dummy Read Dummy Read From IBDR From IBDR Stop Signal From IBDR From IBDR And Store Figure 14-16. Flow-Chart of Typical IIC Interrupt Routine S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 567 Chapter 14 Inter-Integrated Circuit (IICV3) Block Description Caution:When IIC is configured as 10-bit address,the point of the data array in interrupt routine must be reset after it’s addressed. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 568 Chapter 14 Inter-Integrated Circuit (IICV3) Block Description S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 569: Introduction
Timing and Control – consists of registers and control logic for frame clock generation, bias voltage level select, frame duty select, backplane select, and frontplane select/enable to produce the required frame frequency and voltage waveforms. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 570: Features
This is a high level description only, detailed descriptions of operating modes are contained in Section 15.4.2, “Operation in Wait Mode”, and Section 15.4.3, “Operation in Stop Mode”. 15.1.3 Block Diagram Figure 15-1 is a block diagram of the LCD40F4BV3 module. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 571 Chapter 15 Liquid Crystal Display (LCD40F4BV3) Block Description Internal Address/Data/Clocks RTCCLK Timing Prescaler Control 20 bytes Logic LCD Clock Frontplane Voltage Backplane Drivers Generator Drivers BP[3:0] FP[39:0] VLCD Figure 15-1. LCD40F4BV3 Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 572: External Signal Description
15-3. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the LCD40F4BV3 module and the address offset for each register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 573 LCDRAM (Location 14) Read/Write 0x0017 LCDRAM (Location 15) Read/Write 0x0018 LCDRAM (Location 16) Read/Write 0x0019 LCDRAM (Location 17) Read/Write 0x001A LCDRAM (Location 18) Read/Write 0x001B LCDRAM (Location 19) Read/Write 0x001C- Unimplemented 0x001F S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 574: Register Descriptions
FP11BP2 FP11BP1 FP11BP0 FP10BP3 FP10BP2 FP10BP1 FP10BP0 0x000E LCDRAM6 FP13BP3 FP13BP2 FP13BP1 FP13BP0 FP12BP3 FP12BP2 FP12BP1 FP12BP0 0x000F LCDRAM7 FP15BP3 FP15BP2 FP15BP1 FP15BP0 FP14BP3 FP14BP2 FP14BP1 FP14BP0 Figure 15-2. LCD40F4BV3 Register Summary S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 575 Figure 15-2. LCD40F4BV3 Register Summary 15.3.2.1 LCD Control Register 0 (LCDCR0) Module Base + 0x0000 LCDEN LCLK1 LCLK0 BIAS DUTY1 DUTY0 Reset = Unimplemented or Reserved Figure 15-3. LCD Control Register 0 (LCDCR0) Read: anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 576 BIAS Voltage Level Select — This bit selects the bias voltage levels during various LCD operating modes, as BIAS shown in Table 15-9. LCD Duty Select — The DUTY1 and DUTY0 bits select the duty (multiplex mode) of the LCD40F4BV3 driver DUTY[1:0] system, as shown in Table 15-9. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 577 1 LCD operates normally in stop mode. If lcd clock come from 32k osc clock which is not stoped during full stop mode, LCDRSTP=1 will control LCD run in pseudo stop or full stop mode. If lcd clock come from main osc clock, LCDRSTP=1 will control LCD run in pseudo stop mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 578 FP34EN FP33EN FP32EN Reset Figure 15-9. LCD Frontplane Enable Register 4 (LCDFPENR4) These bits enable the frontplane output waveform on the corresponding frontplane pin when LCDEN = 1. Read: anytime Write: anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 579 0x000F FP15BP3 FP15BP2 FP15BP1 FP15BP0 FP14BP3 FP14BP2 FP14BP1 FP14BP0 LCDRAM Reset 0x0010 FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0 LCDRAM Reset I = Value is indeterminate Figure 15-10. LCD RAM (LCDRAM) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 580 FP36BP3 FP36BP2 FP36BP1 FP36BP0 LCDRAM Reset 0x001B FP39BP3 FP39BP2 FP39BP1 FP39BP0 FP38BP3 FP38BP2 FP38BP1 FP38BP0 LCDRAM Reset I = Value is indeterminate Figure 15-10. LCD RAM (LCDRAM) (continued) Read: anytime Write: anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 581: Functional Description
Table 15-8. LCD Clock and Frame Frequency LCD Clock Source clock Prescaler Frame Frequency [Hz] LCD Clock Frequency in Divider Frequency [Hz] LCLK1 LCLK0 1/1 Duty 1/2 Duty 1/3 Duty 1/4 Duty RTCCLK = 32768 RTCCLK = 32000 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 582 The LCD40F4BV3 driver has five modes of operation: • 1/1 duty (1 backplane), 1/1 bias (2 voltage levels) • 1/2 duty (2 backplanes), 1/2 bias (3 voltage levels) • 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 583: Operation In Wait Mode
As a result, after exiting from stop mode, the LCD40F4BV3 driver system clocks will run (if LCDEN = 1) and the frontplane and backplane pins retain the functionality they had prior to entering stop mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 584: Lcd Waveform Examples
Chapter 15 Liquid Crystal Display (LCD40F4BV3) Block Description 15.4.4 LCD Waveform Examples Figure 15-11 through Figure 15-15 show the timing examples of the LCD output waveforms for the available modes of operation. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 585 - BP1, BP2, and BP3 are not used, a maximum of 40 segments are displayed. 1 Frame VLCD VSSX VLCD FPx (xxx0) VSSX VLCD FPy (xxx1) VSSX +VLCD BP0-FPx (OFF) -VLCD +VLCD BP0-FPy (ON) -VLCD Figure 15-11. 1/1 Duty and 1/1 Bias S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 586 BP1-FPx (ON) -VLCD  1/2 -VLCD +VLCD +VLCD  1/2 BP0-FPy (OFF) -VLCD  1/2 -VLCD +VLCD +VLCD  1/2 BP0-FPz (ON) -VLCD  1/2 -VLCD Figure 15-12. 1/2 Duty and 1/2 Bias S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 587 Bias = 1/3:BIAS = 1 = VSSX, V = VLCD * 1/3, V = VLCD * 2/3, V = VLCD - BP2 and BP3 are not used, a maximum of 80 segments are displayed. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 588 BP0-FPy (OFF) -VLCD  1/3 -VLCD  2/3 -VLCD +VLCD +VLCD  2/3 +VLCD  1/3 BP0-FPz (ON) -VLCD  1/3 -VLCD  2/3 -VLCD Figure 15-13. 1/2 Duty and 1/3 Bias S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 589 BP0-FPx (OFF) -VLCD  1/3 -VLCD  2/3 -VLCD +VLCD +VLCD  2/3 +VLCD  1/3 BP1-FPx (ON) -VLCD  1/3 -VLCD  2/3 -VLCD Figure 15-14. 1/3 Duty and 1/3 Bias S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 590: Lcd Clock Inputs & Reset Behavior
LCD. If clock source is OSCCLK_32K, software must wait the OSC startup time before enabling the LCD. If 32K OSC is enabled, it will be always on until a power on reset happens. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 591: Resets
Section 15.3, “Memory Map and Register Definition”. The behavior of the LCD40F4BV3 system during reset is described in Section 15.4.1, “LCD Driver Description”. 15.6 Interrupts This module does not generate any interrupts. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 592 Chapter 15 Liquid Crystal Display (LCD40F4BV3) Block Description S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 593: Introduction
The motor controller can be configured to either 11- or 7-bits resolution mode by clearing or setting the FAST bit. This bit influences all PWM channels. For details, please refer to Section 16.3.2.5, “Motor Controller Duty Cycle Registers”. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 594 Low-Power Modes The behavior of the motor controller in low-power modes is programmable. For details, please refer to Section 16.4.5, “Operation in Wait Mode” Section 16.4.6, “Operation in Stop and Pseudo-Stop Modes”. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 595: Block Diagram
PWM Channel Pair PWM Channel M0C0M Duty Register 0 Comparator M0C0P M0C1M Duty Register 1 Comparator M0C1P M1C0M Duty Register 2 Comparator M1C0P M1C1M Duty Register 3 Comparator M1C1P Figure 16-1. MC10B8C Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 596: External Signal Description
This section provides a detailed description of all registers of the 11-bit 4-channel motor controller module. 16.3.1 Module Memory Map Figure 16-2 shows the memory map of the 11-bit 4-channel motor controller module. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 597 Motor Controller Duty Cycle Register 2 (MCDC2) — Low Byte 0x0026 Motor Controller Duty Cycle Register 3 (MCDC3) — High Byte 0x0027 Motor Controller Duty Cycle Register 3 (MCDC3) — Low Byte S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 598: Register Descriptions
This register controls the operating mode of the motor controller module. Offset Module Base + 0x0000 MCPRE[1:0] MCSWAI FAST DITH MCTOIF Reset = Unimplemented or Reserved Figure 16-3. Motor Controller Control Register 0 (MCCTL0) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 599 This register controls the behavior of the analog section of the motor controller as well as the interrupt enables. Offset Module Base + 0x0001 RECIRC MCTOIE Reset = Unimplemented or Reserved Figure 16-4. Motor Controller Control Register 1 (MCCTL1) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 600 Motor Controller Timer Counter Overflow Interrupt Enable MCTOIE 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the motor controller timer counter overflow interrupt flag (MCTOIF) is set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 601 Programming MCPER to 0x0001 and setting the DITH bit will be managed as if MCPER is programmed to 0x0000. All PWM channels will be shut off after the next period timer counter overflow. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 602 Half H-bridge mode, PWM on MnCxP, MnCxM is released Full H-bridge mode Dual full H-bridge mode Table 16-8. PWM Alignment Mode MCAM[1:0] PWM Alignment Mode Channel disabled Left aligned Right aligned Center aligned S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 603 FAST bit in the control register 0. Offset Module Base + 0x0020 . . . 0x002F Access: User read/write Reset = Unimplemented or Reserved Figure 16-8. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 604 Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active sign, duty cycle, and dither functionality due to the double buffering scheme.  1. Odd duty cycle register: MCDCx+1, x = 2 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 605: Functional Description
MnC0P  MCMCx + 1 MCDCx + 1 PWM Channel x + 1, x = 2 MnC1M MnC1P MCMC0 MCDC0 PWM Channel 0 M0C0M M0C0P MCMC1 MCDC1 PWM Channel 1 M0C1M M0C1P S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 606 While fast mode is enabled (FAST = 1), 8-bit write accesses to the high byte of the duty cycle registers are allowed, because only the high byte of the duty cycle register is used to determine the duty cycle. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 607 S bit has no effect. Released MnC0P PWM Channel x MnC0M PWM Output Released MnC1P PWM Channel x + 1 MnC1M PWM Output Figure 16-11. Typical Quad Half H-Bridge Mode Configuration S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 608 Right aligned (MCAM[1:0] = 10): The output will start inactive (high if RECIRC = 0 and low if RECIRC = 1) and will turn active after the number of counts specified by the difference of the contents of period register and the corresponding duty cycle register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 609 MnC0P (if the PWM channel number is even, n = 0, 1, 2, 3, see Table 16-11) or MnC1P (if the PWM channel number is odd, n = 0, 1, 2, 3). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 610 16-14, and Figure 16-15 illustrate the effect of the RECIRC bit in (dual) full H-bridge modes. RECIRC bit must be changed only while no PWM channel is operated in (dual) full H-bridge mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 611 Figure 16-12. PWM Active Phase, RECIRC = 0, S = 0 Static 0 PWM 0 MnC0P MnC0M Static 0 PWM 0 Figure 16-13. PWM Passive Phase, RECIRC = 0, S = 0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 612 Figure 16-14. PWM Active Phase, RECIRC = 1, S = 0 Static 1 PWM 1 MnC0P MnC0M Static 1 PWM 1 Figure 16-15. PWM Passive Phase, RECIRC = 1, S = 0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 613 10 or 11 Active (Dual) Full 10 or 11 Passive (Dual) Full 10 or 11 Active (Dual) Full 10 or 11 Passive (Dual) Full 10 or 11 Active (Dual) Full 10 or 11 Passive S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 614 PWM period (when the motor controller timer counter = 0x000). The PWM output remains low until the motor controller timer counter matches the 10-bit PWM duty cycle S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 615 Clock Motor Controller Timer Counter PWM Output 1 Period 100 Counts 100 Counts Figure 16-18. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 31, MCPER = 200, RECIRC = 0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 616 Clock Motor Controller Timer Counter PWM Output 1 Period 100 Counts 100 Counts Figure 16-21. PWM Output: DITH = 1, MCAM[1:0] = 11, MCDC = 31, MCPER = 200, RECIRC = 0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 617: Pwm Duty Cycle
MCPRE[1:0] bits in motor controller control register 0 (MCCTL0). The motor controller channel frequency of operation can be calculated using the following formula if DITH = 0: ------------------------------ - Motor Channel Frequency (Hz)  MCPER M S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 618: Output Switching Delay
, is determined by the CD[1:0] bits in the corresponding channel control register (MCMCx) and is selectable between 0, 1, 2, or 3 motor controller timer counter clock cycles. NOTE A PWM channel gets disabled at the next timer counter overflow without notice of the switching delay. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 619: Operation In Wait Mode
PWM frame is finished. The interrupt is cleared by either setting the MCTOIE bit to 0 or to write a 1 to the MCTOIF bit in the motor controller control register 0. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 620: Initialization/Application Information
The period register is cleared after a certain time, which disables the motor controller. The table address is restored and the timer interrupt flag is cleared. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 621: Introduction
— Blanking with no drive — Blanking with drive — Conversion — Integration • Low-power modes 17.1.2 Features • Programmable full step state • Programmable integration polarity • Blanking (recirculation) state • 16-bit integration accumulator register S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 622: Block Diagram
VSSM VSSM reference integrator – – 16-bit accumulator VDDM register 16-bit load register sigma-delta converter 16-bit modulus (analog) VSSM down counter 4:1 MUX 2:1 MUX Bus Clock Figure 17-1. SSD Block Diagram S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 623: External Signal Description
17.2.2 SINM/SINP — Sine Coil Pins for Motor These pins interface to the sine coils of a stepper motor to measure the back EMF for calibration of the pointer reset position. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 624: Memory Map And Register Definition
This section describes in detail all the registers and register bits in the SSDV2 block. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 625 270 angle. For each full step state, Table 17-7 shows the current through each of the two coils, and the coil nodes that are multiplexed to the sigma-delta converter during conversion or integration mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 626 Open Open Open Open Open Close Close Open Open Open Open Open Close Open Open Close Close Open Open Close Open Open Open Open Open Close Close Open Open Open Open Open S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 627 0 Reads of the modulus count register (MDCCNT) will return the present value of the count register. 1 Reads of the modulus count register (MDCCNT) will return the contents of the load register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 628 MCU power consumption. Because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after it is powered up. 0 Sigma-delta converter is powered down. 1 Sigma-delta converter is powered up. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 629 ITG bit is cleared. 17.3.2.4 Stepper Stall Detector Flag Register (SSDFLG) Module Base + 0x0003 MCZIF AOVIF Reset = Unimplemented or Reserved Figure 17-5. Stepper Stall Detector Flag Register (SSDFLG) Read: anytime Write: anytime. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 630 If modulus mode is enabled (MODMC = 1), a write to the MDCCNT register updates the load register with the value written to it. The count register will not be updated with the new value until the next counter S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 631: Functional Description
16-bit signed register. The SSD also has a 16-bit modulus down counter to monitor blanking and integration times. DC offset compensation is implemented when using the modulus down counter to monitor integration times. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 632: Return To Zero Modes
For counter clockwise rotation (CCW), the STEP value is incremented 0, 1, 2, 3, 0 and so on, and for a clockwise rotation the STEP value is decremented 3, 2, 1, S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 633 Figure 17-11. Current Flow when STEP = 0, DCOIL = 1, ITG = 0, RCIR = 0 Figure 17-12 shows the current flow in the SIN and COS H-bridges when STEP = 1, DCOIL = 1, ITG = 0 and RCIR = 1. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 634 Figure 17-13. Current flow when STEP = 2, DCOIL = 1, ITG = 1 Figure 17-14 shows the current flow in the SIN and COS H-bridges when STEP = 3, DCOIL = 1 and ITG = 1. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 635 Chapter 17 Stepper Stall Detector (SSDV2) Block Description VDDM VDDM COSP COSM SINP SINM VSSM VSSM Figure 17-14. Current flow when STEP = 3, DCOIL = 1, ITG = 1 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 636: Operation In Low Power Modes
• Clearing SDCPU bit powers down the sigma-delta converter. 17.4.4 Stall Detection Flow Figure 17-15 shows a flowchart and software setup for stall detection of a stepper motor. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 637 MDCCNT = 0x0000? or MCZIF = 1? End of Integration? ITGACC < Threshold (RAM value)? Stall Detection? 1. Clear MCZIF. Disable SSD 2. Clear MCEN. 3. Clear ITG. 4. Clear RTZE; clear SDCPU. Figure 17-15. Return-to-Zero Flowchart S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 638 Chapter 17 Stepper Stall Detector (SSDV2) Block Description S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 639: Introduction
— Minute — Hour • Five periodic interrupts • Built-in compensation mechanism for frequency error compensation 18.2.1 Modes of Operation This section defines the RTC operation in stop, wait and background debug modes. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 640: Block Diagram
In freeze mode(BDM active), depend on the bit FRZ in RTCCTL3, RTC will be stop or run continue. 18.2.2 Block Diagram The block diagram for the RTC module is shown in Figure 18-1. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 641: External Signal Description
Hour Counter Register Figure 18-1. Real-Time Counter with Calendar (RTC) Block Diagram 18.3 External Signal Description 18.3.1 OSCCLK The OSCCLK is 4-16MHZ main OSC output. 18.3.2 OSCCLK_32K The OSCCLK_32K is 32.768K OSC output. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 642: Ircclk
0x0001 CLKS- CLKS- RTCPS3 RTCPS2 RTCPS1 RTCPS0 RTCCTL2 0x0002 CALS RTCCTL3 RTCWE1 CWE0 0x0003 HRIE MINIE SECIE COMPIE TB0IE RTCCTL4 CDLC 0x0004 MINF SECF COMPF TB0F RTCS1 0x0005 RTCCCR 0x0006 RTCMODH RTCMODH S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 643: Rtc Control Register 1(Rtcctl1)
0 RTC function is disabled. 1 RTC function is enabled. RTC Compensation Enable— The read/write bit enables the clock compensation mechanism for clock COMPE frequency errors. 0 Compensation mechanism is disabled. 1 Compensation mechanism is enabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 644: Rtc Control Register 2 (Rtcctl2)
18.4.3 RTC Control Register 3 (RTCCTL3) The RTCCTL3 contains the write protection configure bits (RTCWE1, RTCW0), the compensation data setting ready bit. CALS RTCWE1 RTCWE0 Reset: Figure 18-4. RTC Control Register 3(RTCCTL3) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 645: Rtc Control Register 4 (Rtcctl4)
Second Interrupt Enable — This read/write bit enables second interrupts. If SECIE is set, then an interrupt is SECIE generated when SECF is set. 0 Second interrupt request is disabled. 1 Second interrupt request is enabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 646: Rtc Status Register 1 (Rtcs1)
SECF generates a CPU interrupt request. Writing a logic 0 has no effect. Writing a logic 1 clears the bit and the second interrupt request. Reset clears SECF to 0. 0 No second counter increment. 1 Second counter increment. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 647: Rtc Compensation Configure Register (Rtcccr)
M+1 modulo value do not happen. Refer to Section Table 18-14., “the CCS, precision and Q value” 18.4.7 RTC Counter Register (RTCCNT) RTCCNT is the read-only value of the current RTC count of the 16-bit counter. RTCCNTH POR: S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 648: Rtc Modulo Register (Rtcmod)
0 to 59 to this register has no effect. This register is write-protected, writing this register should follow write-protect mechanism section. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 649: Rtc Minute Register (Rtcminr)
0 to 23 to this register has no effect. This register is write-protected, writing this register should follow write-protect mechanism section. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 650: Functional Description
(RTCSECF), minute (RTCMINF) and hour (RTCHRF). A CPU interrupt request is generated if the corresponding enable bit (SECIE, MINIE and HRIE) is also set. 18.5.3 Interrupts In addition to the second, minute and hour periodic interrupts generated by the clock functions, the S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 651: Rtc Clock Compensation
32833 first. The fraction value will be 0.536, and we can get CCS=0, Q=3 or CCS=1, Q=8 or CCS=2, Q=16 or CCS=3, Q=32. Second example, if the RTC clock is from OSCLK and it has -2000PPM frequence drift due to the crystal S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 652: Calendar Register And Bit Write Protection
Write any value other than 10 to RTWE RTCWE = 10 Note: Reading RTCWE[1:0] always return 00. RTCWE = 00 Write any value other than 00 to RTWE RTCWE = 11 RTCWE 01 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 653: Load Buffer Register
1 Hz clock to the other timer input pin. The calibration software can then take simultaneous measurements of both signals using the input capture function of the timer to calculate S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 654: S12Zvhy/S12Zvhl Family Reference Manual Rev. 1.05 Freescale Semiconductor
Perform the RTC calibration at production for each device, get the base frequency offset. • Perform the RTC compensation periodically after enabling the RTC. — Measure the external temperature — Lookup compensation value in lookup table — Load the compensation value into RTC S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 655: Introduction
Separate or mixed frequency and amplitude outputs for flexibility in external hardware variations • Attack/decay function which can increase/decrease sound amplitude automatically without CPU interaction, including linear, gong and exponential attack/decay operation 19.1.2 Block Diagram Figure 19-1 shows the block diagram for SSG block. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 656: External Signal Description
External amplifier is required due to the limited driving capability of SGT pad Figure 19-1. SSG Block Diagram 19.2 External Signal Description 19.2.1 Tone output signal of SSG, which can be a single output tone signal or a tone combined with amplitude encoding. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 657: Memory Map And Register Definition
This section describes in detail all the registers and register bits in the SSG module. Register Bit 7 Bit 0 Name 0x0000 SSGE SSGCR 0x0001 ADM[1:0] SSGADC 0x0002 PS10 SSGPSH 0x0003 SSGPSL = Unimplemented or Reserved Figure 19-2. The SSG Register Summary (Sheet 1 of 3) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 658 AMPB6 AMPB5 AMPB4 AMPB3 AMPB2 AMP1 AMPB0 SSGAMPBL 0x0012 DCNT7 DCNT6 DCNT5 DCNT4 DCNT3 DCNT2 DCNT1 DCNT0 SSGDCNT = Unimplemented or Reserved Figure 19-2. The SSG Register Summary (Sheet 2 of 3) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 659 0 SSG is disabled. All counters will be reset to 0, input clock will be gated. 1 SSG is enabled. SSG Output Mode Selection 0 SGT output tone mixed with amplitude. 1 SGT output tone solely. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 660 00 Select linear attack/decay operation. 01 Select gong attack/decay operation. 10 Select exponential attack/decay operation. 11 Reserved. SSG Decay or attack Selection 0 Select amplitude attack function. 1 Select amplitude decay function. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 661 PWM cycle period. Table 19-5. Prescaler Clock Divider Divided Clock Frequency From Divide Ratio SSGPS[10:0] 32MHz Clock Source 125KHz 0xFF 124.514KHz 0x100 124.031KHz 0x101 123.552KHz~15.633KHz 259~2047 0x102~0x7FE 15.625KHz 2048 0x7FF S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 662 Adjacent Tone Prescaler Clock Tone Frequency SSGTONE[9:0] Frequency Gap Frequency Range Range 15KHz 100Hz~7.5KHz 0x4A~0x0 1.351Hz~3750Hz 30KHz 100Hz~7.5KHz 0x95~0x1 0.671Hz~2500Hz 60KHz 100Hz~7.5KHz 0x12B~0x3 0.334Hz~1500Hz 90KHz 100Hz~7.5KHz 0x1C1~0x5 0.223~1072Hz 125KHz 100Hz~7.813KHz 0x270~0x7 0.16Hz~1115Hz S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 663 0, otherwise amplitude will always be 0 and gong attack operation will never end. 19.3.2.6 SSG Amplitude Adjustment (SSGAA) The SSGAA is amplitude adjustment register. Module Base + 0x0008 AA10 Reset Figure 19-11. SSG Amplitude Adjustment (SSGAAH) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 664 SSGAT contains the amplitude threshold. Module Base + 0x000A AT10 Reset Figure 19-13. SSG Amplitude Threshold (SSGATH) Module Base + 0x000B Reset Figure 19-14. SSG Amplitude Threshold (SSGATL) Read: Anytime Write: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 665 RDR of SSGCR is 1, or SSG will stop if RDR of SSGCR is 0. 19.3.2.9 SSG Interrupt Enable (SSGIE) The SSGIE controls the enable of the interrupt. Module Base + 0x000D RNDIE Reset Figure 19-16. SSG Interrupt Enable Register (SSGIE) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 666 0 The SSG is not ready to config the next sound data. 1 The SSG is ready to config the next sound data. 19.3.2.11 Buffer Register of SSGAMP (SSGAMPB) The SSGAMPB is the buffer register of SSGAMP. It determines amplitude directly. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 667 The SSGDCNT is tone duration counter which contains tone cycle number. It is triggered by the negedge of tone signal. Module Base + 0x0012 DCNT7 DCNT6 DCNT5 DCNT4 DCNT3 DCNT2 DCNT1 DCNT0 Reset Figure 19-20. SSG Tone Duration Counter (SSGDCNT) Read: Anytime Write: Anytime S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 668: Functional Description
: RDR is the RDR bit of SSGCR Pcounter is the prescaler counter A is value of SSGAMP buffer P is the value of SSGPS buffer Figure 19-21. SSG Amplitude Generation S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 669: Ssg Tone Generation
ADE is set, decay function will be enabled. If ADE is cleared, attack/decay function will be disabled. The attack/decay function implements sound volume automatic increase/decrease with a small number of CPU interventions. Attack/decay function includes linear operation, gong operation and exponential operation. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 670 SSGAMPB = SSGAMP; SSGAMPB = SSGAMPB - SSGAA_buf; } While (SSGAMPB > AT_buf) Where : AT_buf is the internal buffer of amplitude threshold register SSGAT. SSGAA_buf is the internal buffer of SSGAA. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 671 AMP_int = AMP_int - (AMP_int >> 5); SSGAMPB = AMP_int >> 5; } While (SSGAMPB > AT_buf) where : AMP_int is a 16 bit internal register. AT_buf is the internal buffer of amplitude threshold register SSGAT. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 672: Ssg Start And Stop
The RDR of SSGCR can also stop the SSG, when reload occurs while the RDR is cleared, SSG will stop with all counters cleared, and the interrupt flag (RNDI of SSGIF) will be set. When the RDR is set again, the SSG will restart. Refer to Figure 19-23 Figure 19-24. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 673: Register Reload
AMPB is the initial value reload from SSGAMP register AMPB_x is the interim value of SSGAMPB in attack/decay operation AMPB_T is the value of SSGAT buffer RDR is the RDR bit of SSGCR register Figure 19-23. Attack/decay Mode Register Reload S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 674: Ssg Output Control
When the RNDI of SSGIF and RNDIE of SSGIE are all set, interrupt will be generated. Besides normal reload interrupt, RNDI will be set when SSG start with RDR set, so the second configuration data can be set base on reload interrupt. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 675: Introduction
Memory Map and Register Definition This section provides a detailed description of all memory and registers for the SRAM_ECC module. 20.2.1 Register Summary Figure 20-1 shows the summary of all implemented registers inside the SRAM_ECC module. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 676 0x0009 DPTR[7:1] ECCDPTRL 0x000A - 0x000B Reserved 0x000C DDATA[15:8] ECCDDH 0x000D DDATA[7:0] ECCDDL 0x000E DECC[5:0] ECCDE 0x000F ECCDRR ECCDW ECCDR ECCDCMD = Unimplemented, Reserved, Read as zero Figure 20-1. SRAM_ECC Register Summary S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 677: Register Descriptions
Table 20-3. ECCIE Field Description Field Description Single bit ECC Error Interrupt Enable — Enables Single ECC Error interrupt. SBEEIE 0 Interrupt request is disabled 1 Interrupt will be requested whenever SBEEIF is set S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 678 Single bit ECC Error Interrupt Flag — The flag is set to 1 when a single bit ECC error occurs. SBEEIF 0 No occurrences of single bit ECC error since the last clearing of the flag 1 Single bit ECC error occurs since the last clearing of the flag S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 679 There is no additional monitoring of the register content, therefore the SW must make sure that the address value points to the system memory space. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 680 ECC Debug ECC — This register contains the raw ECC value which will be written into the system memory DECC[5:0] during a debug write command or the ECC read value from the debug read command. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 681: Functional Description
Table 20-9. Memory access cycles access Memory Access type Internal operation Error indication error cycle content 2 and 4 byte aligned write write to memory new data access S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 682: Aligned 2 And 4 Byte Memory Write Access
If the module detects a double bit ECC error during the read cycle, then the write access to the memory is blocked and the initiator module is informed about the error. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 683: Memory Read Access
SRAM access is possible and the RDY status bit is set. 20.3.5 Interrupt handling This sections describes the interrupts generated by the SRAM_ECC module and their individual sources, Vector addresses and interrupt priority are defined by MCU level. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 684: Ecc Algorithm
DPTR. During this access, the raw data DDATA and the ECC value DECC are written direct into the system memory. If the debug write access is done the ECCDW register bit is cleared. The debug write S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 685 During the debug read access no ECC check is performed, so that no single or double bit ECC error indication are activated. If the ECCDW and the ECCDR bits are set at the same time, then only the debug write access is performed. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 686 Chapter 20 ECC Generation module (SRAM_ECCV1) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 687: Chapter 21 64 Kb Flash Module (S12Zftmrz64K2Kv2)
Section 21.4.7.12 and MLOADF Section 21.4.7.13 FCCOB1 to FCCOB2 V02.09 19 Aug 2013 - Updated table of valid commands regarding Secured Special Singlechip mode (Table 21-29) - Updated text under Section 21.5.2 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 688: Introduction
EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 689: Features
Interrupt generation on Flash command completion and Flash error detection • Security mechanism to prevent unauthorized access to the Flash memory 21.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 21-1. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 690: External Signal Description
Clock Divider FCLK Memory Controller EEPROM 1K x22 sector 0 sector 1 sector 511 Figure 21-1. FTMRZ64K2K Block Diagram 21.2 External Signal Description The Flash module contains no signals that connect off-chip. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 691: Memory Map And Registers
Three separate memory regions, one growing upward from global address 0xFF_8000 in the Flash memory (called the lower region), one growing downward from global address 0xFF_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 692 Section 21.3.2.2, “Flash Security Register (FSEC)” 1. 0xFF_FE08-0xFF_FE0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0xFF_FE0A - 0xFF_FE0B reserved field should be programmed to 0xFF. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 693 Protection Fixed End Flash Protected/Unprotected Higher Region 0xFF_E000 2, 4, 8, 16 KB 0xFF_F000 0xFF_F800 Flash Configuration Field P-Flash END = 0xFF_FFFF 16 bytes (0xFF_FE00 - 0xFF_FE0F) Figure 21-2. P-Flash Memory Map S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 694 Reserved 0x1F_9800 – 0x1F_BFFF 10,240 Reserved 0x1F_C000 – 0x1F_C0FF P-Flash IFR (see Table 21-5) 0x1F_C100 – 0x1F_C1FF Reserved. 0x1F_C200 – 0x1F_FFFF 15,872 Reserved. 1. See Section 21.4.4 for NVM Resources Area description. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 695: Register Descriptions
& Name FDIVLD 0x0000 FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 FCLKDIV KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 0x0001 FSEC 0x0002 CCOBIX2 CCOBIX1 CCOBIX0 FCCOBIX Figure 21-4. FTMRZ64K2K Register Summary S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 696 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOB1HI 0x000F CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 FCCOB1LO 0x0010 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 FCCOB2HI Figure 21-4. FTMRZ64K2K Register Summary (continued) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 697 All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 698 39.6 0x26 13.6 14.6 0x0D 39.6 40.6 0x27 14.6 15.6 0x0E 40.6 41.6 0x28 15.6 16.6 0x0F 41.6 42.6 0x29 16.6 17.6 0x10 42.6 43.6 0x2A 17.6 18.6 0x11 43.6 44.6 0x2B S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 699 Table 21-9. FSEC Field Descriptions Field Description 7–6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 21-10. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 700 Offset Module Base + 0x0002 CCOBIX[2:0] Reset = Unimplemented or Reserved Figure 21-7. FCCOB Index Register (FCCOBIX) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 701 1 Wait-State switch is complete, Flash reads are already working according to the value set on FCNFG[WSTAT] 21.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt, control generation of wait-states and forces ECC faults on Flash array read access from the CPU. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 702 21.4.3. The WSTAT[1:0] bits should not be updated while the Flash is executing a command (CCIF=0); if that happens the value of this field will not change and no action will take place. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 703 The FERCNFG register enables the Flash error interrupts for the FERSTAT flags. Offset Module Base + 0x0005 SFDIE Reset = Unimplemented or Reserved Figure 21-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 704 Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller MGBUSY 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 705 2. There is a one cycle delay in storing the ECC DFDF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 706 Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area FPHS[1:0] in P-Flash memory as shown inTable 21-21. The FPHS bits can only be written to while the FPHDIS bit is set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 707 Flash memory at global address 0xFF_FE0C during the reset sequence, it can be changed by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 708 FLASH START 0xFF_8000 0xFF_FFFF Protected region with size Unprotected region defined by FPLS Protected region Protected region with size not defined by FPLS, FPHS defined by FPHS Figure 21-14. P-Flash Protection Scenarios S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 709 EEPROM protection byte in the Flash configuration field at global address 0xFF_FE0D located in P-Flash memory (see Table 21-4) as indicated by reset condition F in Table 21-25. To change the S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 710 The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. 111111 0x10_0000 – 0x10_07FF 2,048 bytes 21.3.2.11 Flash Option Register (FOPT) The FOPT register is the Flash option register. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 711 All bits in the FRSV1 register read 0 and are not writable. 21.3.2.13 Flash Common Command Object Registers (FCCOB) The FCCOB is an array of six words. Byte wide reads and writes are allowed to the FCCOB registers. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 712 Offset Module Base + 0x000F CCOB[7:0] Reset Figure 21-21. Flash Common Command Object 1 Low Register (FCCOB1LO) Offset Module Base + 0x0010 CCOB[15:8] Reset Figure 21-22. Flash Common Command Object 2 High Register (FCCOB2HI) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 713 Offset Module Base + 0x0014 CCOB[15:8] Reset Figure 21-26. Flash Common Command Object 4 High Register (FCCOB4HI) Offset Module Base + 0x0015 CCOB[7:0] Reset Figure 21-27. Flash Common Command Object 4 Low Register (FCCOB4LO) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 714 Table 21-27. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Register Byte FCCOB Parameter Fields (NVM Command Mode) FCMD[7:0] defining Flash command FCCOB0 Global address [23:16] Global address [15:8] FCCOB1 Global address [7:0] Data 0 [15:8] FCCOB2 Data 0 [7:0] S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 715: Functional Description
Reference Manual for details). Forcing the DFDF status bit by setting FDFD (see Section 21.3.2.5) has effect only on the DFDF status bit value and does not result in an invalid access. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 716: Internal Nvm Resource
IFR is an internal NVM resource readable by CPU . The IFR fields are shown in Table 21-5. The NVM Resource Area global address map is shown in Table 21-6. 21.4.5 Flash Command Operations Flash command operations are used to modify Flash memory contents. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 717 Flash command has completed. Upon completion, the Memory Controller will return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic command write sequence is shown in Figure 21-30. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 718 More Parameters? Write: FSTAT register (to launch command) Clear CCIF 0x80 Read: FSTAT register Bit Polling for Command Completion CCIF Set? Check EXIT Figure 21-30. Generic Flash Command Write Sequence Flowchart S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 719  0x13 Protection Override 1. Unsecured Normal Single Chip mode 2. Unsecured Special Single Chip mode. 3. Secured Normal Single Chip mode. 4. Secured Special Single Chip mode.Please refer to Section 21.5.2. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 720 Supports a mode to temporarily override Protection configuration (for P-Flash and/or 0x13 Override EEPROM) by verifying a key. 21.4.5.5 EEPROM Commands Table 21-31 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 721: Allowed Simultaneous P-Flash And Eeprom Operations
Even if the simultaneous operation is marked as not allowed the Flash will report an illegal access only in the cycle the read collision actually happens, maximizing the time the array is available for reading. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 722: Flash Command Description
Cumulative programming of bits within a Flash word or phrase is not allowed. 21.4.7.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and EEPROM blocks have been erased. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 723 Set if any errors have been encountered during the read or if blank check failed. Set if any non-correctable errors have been encountered during the read or if MGSTAT0 blank check failed. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 724 Program Once reserved field to avoid code runaway. Table 21-39. Read Once Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x04 Not Required FCCOB1 Read Once phrase index (0x0000 - 0x0007) FCCOB2 Read Once word 0 value S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 725 Global address [15:0] of phrase location to be programmed FCCOB2 Word 0 program value FCCOB3 Word 1 program value FCCOB4 Word 2 program value FCCOB5 Word 3 program value 1. Global address [2:0] must be 000 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 726 Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 727 The functionality of the Erase All Blocks command is also available in an uncommanded fashion from the soc_erase_all_req input pin on the Flash module. Refer to the Reference Manual for information on control of soc_erase_all_req. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 728 Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 729 Set if the selected P-Flash sector is protected MGSTAT1 Set if any errors have been encountered during the verify operation Set if any non-correctable errors have been encountered during the verify MGSTAT0 operation S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 730 Table 21-54. Verify Backdoor Access Key Command FCCOB Requirements Register FCCOB Parameters FCCOB0 0x0C Not required FCCOB1 Key 0 FCCOB2 Key 1 FCCOB3 Key 2 FCCOB4 Key 3 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 731 EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only. Valid margin level settings for the Set User Margin Level command are defined in Table 21-57. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 732 Margin level setting. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the field margin level for the targeted block and then set the CCIF flag. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 733 If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 734 The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 735 Table 21-66. Erase EEPROM Sector Command FCCOB Requirements Register FCCOB Parameters Global address [23:16] to identify FCCOB0 0x12 EEPROM block Global address [15:0] anywhere within the sector to be erased. FCCOB1 Section 21.1.2.2 for EEPROM sector size. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 736 Protection Update Protection register selection Selection code [1:0] Update P-Flash protection bit 0 0 - keep unchanged (do not update) 1 - update P-Flash protection with new FPROT value loaded on FCCOB S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 737 Set if Protection Update Selection[1:0] = 00 (in case of CCOBIX[2:0] = 010 or 011) FSTAT Set if Protection Update Selection[1:0] = 00, CCOBIX[2:0] = 001 and a valid comparison key is loaded as a command parameter. FPVIOL None MGSTAT1 None MGSTAT0 None S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 738: Interrupts
21.4.9 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 21.4.8, “Interrupts”). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 739: Stop Mode
The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 740: Unsecuring The Mcu In Special Single Chip Mode Using Bdm
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 741: Introduction
BSESE takes precedence over BSUSE. BSEAE takes precedence over BSUAE. 2. Stop mode During stop mode operation the path from the VSENSE pin through the resistor chain to ground is opened and the low voltage sense features are disabled. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 742: Block Diagram
This pin can be connected to the supply (Battery) line for voltage measurements. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC or to a S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 743: Vsup — Voltage Supply Pin
Memory Map and Register Definition This section provides the detailed information of all registers for the BATS module. 22.3.1 Register Summary Figure 22-2 shows the summary of all implemented registers inside the BATS module. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 744: Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Unused bits read back zero. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 745 BATS VSENSE Level Sense Enable — This bit connects the VSENSE pin through the resistor chain to ground BSESE and enables the Voltage Level Sense features measuring BVLC and BVHC.Setting this bit will clear bit BSUSE 0 Level Sense features disabled 1 Level Sense features enabled NOTE S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 746 + two bus cycles the measured EN_UNC value is invalid. This is to let internal nodes be charged to correct value. BVHIE, BVLIE might be cleared for this time period to avoid false interrupts. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 747 V (falling edge) or V (rising edge) measured LBI_A measured LBI_D V V (falling edge) or V (rising edge) measured LBI_A measured LBI_D Figure 22-5. BATS Voltage Sensing HBI_A HBI_D LBI_D LBI_A S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 748 BATS Interrupt Flag Register (BATIF) 22.3.2.4 Module Base + 0x0003 Access: User read/write BVHIF BVLIF Reset = Unimplemented Figure 22-7. BATS Interrupt Flag Register (BATIF) 1. Read: Anytime Write: Anytime, write 1 to clear S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 749: Functional Description
In a typical application, the module could be used as follows: The voltage at VSENSE is observed via usage of the interrupt feature (BSESE=1, BVHIE=1), while the VSUP pin voltage is routed to the ADC to allow regular measurement (BSUAE=1). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 750: Interrupts
BVLC is set. BVLC status bit indicates that a low voltage at the selected pin is present. The Low Voltage Interrupt flag (BVLIF) is set to 1 when the Voltage Low Condition (BVLC) changes state . The S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 751 Voltage Interrupt flag (BVHIF) is set to 1 when a Voltage High Condition (BVHC) changes state. The Interrupt flag BVHIF can only be cleared by writing a 1. If the interrupt is enabled by bit BVHIE the module requests an interrupt to MCU (BATI). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 752 Chapter 22 Supply Voltage Sensor - (BATSV2) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 753: Introduction
The LIN Physical Layer is designed to meet the LIN Physical Layer 2.2 specification from LIN consortium. 23.1.1 Features The LIN Physical Layer module includes the following distinctive features: • Compliant with LIN Physical Layer 2.2 specification. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 754: Modes Of Operation
LIN Physical Layer sends a wake-up pulse to the SCI, which requests a wake-up interrupt. (This feature is only available if the LIN Physical Layer is routed to the SCI). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 755: Block Diagram
& % +" #$ - , * .* * * Figure 23-1. LIN Physical Layer Block Diagram NOTE The external 220 pF capacitance between LIN and LGND is strongly recommended for correct operation. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 756: S12Zvhy/S12Zvhl Family Reference Manual Rev. 1.05 Freescale Semiconductor
In standby mode this output is disabled, and sends only a short pulse in case the wake-up functionality is enabled and a valid wake-up pulse was received in the LIN Bus. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 757: Memory Map And Register Definition
Reserved Reserved 0x0003 LPDTDIS LPSLR1 LPSLR0 LPSLRM 0x0004 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LPDT 0x0005 LPSR 0x0006 LPDTIE LPOCIE LPIE 0x0007 LPDTIF LPOCIF LPIF Figure 23-2. Register Summary S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 758: Register Descriptions
The routing of the LPTxD input is done in the Port Inetrgation Module (PIM). Please refer to the PIM chapter of the device Reference Manual for more info. Port LP Data Bit 0 — Read-only bit. The LIN Physical Layer LPRxD output state can be read at any time. LPDR0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 759 LIN Pullup Resistor Enable — Selects pullup resistor. LPPUE 0 The pullup resistor is high ohmic (330 k).   1 The 34 k pullup is switched on (except if LPE=0 or when in standby mode with LPWUE=0) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 760 LIN Slew Rate Mode Register (LPSLRM) Module Base + Address 0x0003 Access: User read/write LPDTDIS LPSLR1 LPSLR0 Reset = Unimplemented Figure 23-6. LIN Slew Rate Mode Register (LPSLRM) 1. Read: Anytime Write: Only in shutdown mode (LPE=0) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 761 Table 23-6. Reserved Register Field Description Field Description These reserved bits are used for test purposes. Writing to these bits can alter the module functionality. Reserved S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 762 LPTDIF is set again after attempting to clear it. 0 If there was a TxD-dominant timeout, LPTxD has ceased to be dominant after the timeout. 1 LPTxD is still dominant after a TxD-dominant timeout. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 763 0 Interrupt request is disabled. 1 Interrupt is requested if LPDTIF bit is set. LIN transmitter Overcurrent Interrupt Enable — LPOCIE 0 Interrupt request is disabled. 1 Interrupt is requested if LPOCIF bit is set. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 764 If the overcurrent is still present or LPTxD is dominant after clearing the flag, the transmitter stays disabled and this flag is set again (see23.4.4.1 Overcurrent Interrupt). If interrupt requests are enabled (LPOCIE= 1), LPOCIF causes an interrupt request. 0 No overcurrent event has occurred. 1 Overcurrent event has occurred. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 765: Functional Description
A stronger external pullup resistor might be necessary to sustain communication speeds up to 250 kbit/s. The LIN signal (and therefore the receive LPRxD signal) might not be symmetrical for high baud rates with high loads on the bus. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 766: Modes
If LPWUE is not set, no wake up feature is available and the standby mode has the same electrical properties as the shutdown mode. This allows a low-power consumption of the device in stop mode if the wake-up feature is not needed. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 767 SCI interrupt, then the SCI interrupt will execute first). It is up to the software to decide what to do in this case because the LIN Physical Layer can not guarantee it was a valid wake-up pulse. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 768 # $ " ! " ! % % ! " ! " ! # $ " ! Figure 23-11. LIN Physical Layer Mode Transitions S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 769: Interrupts
2 IRC periods (2 us) + 3 bus periods If the bit LPOCIE is set in the LPIE register, an interrupt is requested. Figure 23-12 shows the different scenarios for overcurrent interrupt handling. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 770 To re-enable the transmitter then, the LPDTIF flag must be cleared (by writing a 1). NOTE Please make sure that LPDTIF=1 before trying to clear it. It is not allowed to try to clear LPDTIF if LPDTIF=0 already. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 771 ! "! ! ! # ! "! ! ! "! Figure 23-13. TxD-dominant timeout interrupt handling S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 772: Application Information
— If the receiver must remain enabled, set the LIN Physical Layer into receive only mode instead. 2. Do all required configurations (SCI, etc.) to re-enable the transmission. 3. Wait for a transmit bit (this is needed to successfully re-enable the transmitter). S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 773 7. Wait for a minimum of a transmit bit before beginning transmission again. If there is a problem re-enabling the transmitter, then the error flag will be set again during step 3 and the ISR will be called again. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 774 Chapter 23 LIN Physical Layer (S12LINPHYV2) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 775: A.1 General
T:Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. • D:Those parameters are derived mainly from simulations. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 776: A.1.2 Pins
They have nominal voltages above the standard 5V I/O voltage range. A.1.2.3 Main Oscillator If the designated PE0 (EXTAL) and PE1 (XTAL) pins are configured for external oscillator operation then these pins have a nominal voltage of 1.8V. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 777: A.1.3 Current Injection
Figure A-1. Current Injection on GPIO Port if V > V VSUP Voltage Regulator Pad Driver VDDX Load Load > V VSSX VSSA S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 778: A.1.4 Absolute Maximum Ratings
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 779: A.1.6 Operating Conditions
Latch-up Current of LIN , VSENSET and BCTL at T= 27 C +100 positive -100 negative A.1.6 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 780: A.1.7 Power Dissipation And Thermal Characteristics
The average chip-junction temperature (T obtained from:     Junction Temperature, [C  Ambient Temperature, [C  Total Chip Power Dissipation, [W]  Package Thermal Resistance, [C/W] S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 781 This power component is included in P is subtracted from overall MCU power dissipation P Power dissipation of LINPHY Figure A-2. Supply Currents Overview VBAT RBATP VSUP BCTL VDDA VDDX VDDX[3:1] VDDM VSSX/A/M GPIO S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 782 4. Junction to ambient thermal resistance,  was simulated to be equivalent to the JEDEC specification JESD51-7 in a horizontal configuration in natural convection. 1. The values for thermal resistance are achieved by package simulations S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 783: A.1.8 I/O Characteristics
C Port U Output Rise Time =5V, 10% to 90% of V Cload 47pF connected to GND, slew disabled — — Rload=1K connected to GND, slew enabled Rload=1K connected to VDD, slew enabled S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 784 1/f D IRQ pulse width, edge-sensitive mode (STOP) in — — number of bus clock cycles of period 1/f 1. Parameter only applies in stop or pseudo stop mode. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 785: A.1.9 Supply Currents
PLLSEL=1, CSAD=0 CPMUOSC OSCE=0, Reference clock for PLL is f trimmed to 1MHz irc1m API settings for STOP current measurement CPMUAPICTL APIEA=0, APIFE=1, APIE=0 CPMUAPITR trimmed to >=10Khz CPMUAPIRH/RL set to 0xFFFF S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 786 Table A-12 Rating Symbol Unit Run Current SUPR Wait Current SUPW Table A-14. Stop Current Characteristics Conditions are: V =12V Rating Symbol Unit Stop Current all modules off A = -40C SUPS S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 787: A.1.10 Adc Conversion Result Reference
Value Unit Regulator supply voltage VSUP I/O supply voltage DDX, A,M ADC clock ADCCLK ADC sample time ADC clock cycles Bus frequency C Ambient temperature Code execution from RAM NVM activity none S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 788 Appendix A MCU Electrical Specifications S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 789: B.1 Adc Operating Characteristics
Factors Influencing Accuracy Source resistance, source capacitance and current injection have an influence on the accuracy of the ADC. A further factor is that PortAD pins that are configured as output drivers switching. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 790 Total input capacitance Sampling — — Input internal Resistance k C Disruptive analog input current -2.5 — C Coupling ratio positive current injection — — 1E-4 C Coupling ratio negative current injection — — 5E-3 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 791: B.1.2 Adc Accuracy
------------------------- - 1 – 1LSB The integral non-linearity (INL) is defined as the sum of all DNLs: –  INL n   DNL i   -------------------- - n – 1LSB S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 792 $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 Ideal Transfer Curve 10-Bit Transfer Curve 8-Bit Transfer Curve 95 100 105 110 115 120 5000 + Figure B-1. ADC Accuracy Definitions S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 793 1. The 8-bit mode operation is structurally tested in production test. Absolute values are tested in 10-bit mode. 2. Absolute error includes the quantization error which is inherently 1/2 count for any A/D converter. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 794 Appendix B ADC Electricals S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 795: C.1 Reset, Oscillator And Pll
        max 1  ---------------------- - ---------------------- -  – –     The following equation is a good fit for the maximum jitter: S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 796 Time to lock 150 + lock 256/f Jitter fit parameter 1 P PLL Clock Monitor Failure assert frequency 0.45 PMFA 1. % deviation from target frequency 2. f = 1MHz, f = 32MHz S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 797: Appendix D Irc Electrical Specifications
Appendix D IRC Electrical Specifications Table D-1. IRC electrical characteristics Num C Rating Symbol Unit Junction Temperature - 40 to 150 Celsius 0.987 1.013 IRC1M_TRIM Internal Reference Frequency, factory trimmed S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 798: Appendix D
Appendix D IRC Electrical Specifications S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 799: E.1 Lcd Driver
Simplified output voltage transients are shown in Figure E-2.. The shown transients emphasize the spikes and the voltage recovery. They are not to scale. The buffer output S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 800 GND or VLCD. resistive constant current 2/3VLCD 1/2VLCD 1/3VLCD Figure E-2. V transients (not to scale) 1/3, 1/2 or 2/3 VLCD BP/FP resistive region current source BP/FP region Figure E-3. buffer output characteristic S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 801: F.1 Mscan Electrical Characteristics
Conditions are shown in Table F-1. unless otherwise noted Num C Rating Symbol Unit s P MSCAN wakeup dominant pulse filtered — — s P MSCAN wakeup dominant pulse pass — — S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 802 Appendix F MSCAN Electrical Specifications S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 803: G.1 Nvm Timing Parameters
13.63 436.00 MLOADF Erase Verify EEPROM Section 0.02 0.02 0.07 2.33 DRD1SEC Program EEPROM (1 Word) 1657 0.12 0.12 0.28 6.71 DPGM_1 Program EEPROM (2 Word) 2660 0.21 0.22 0.47 10.81 DPGM_2 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 804: G.2 Nvm Reliability Parameters
C EEPROM number of program/erase cycles (-40C  tj  150C 100K 500K — Cycles FLPE 1. T does not exceed 85C in a typical temperature profile over the lifetime of a consumer, industrial or automotive application. Javg S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 805 25C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618 3. Spec table quotes typical endurance evaluated at 25C for this product family. For additional information on how Freescale defines Typical Endurance, please refer to Engineering Bulletin EB619. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 806 Appendix G NVM Electrical Parameters S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 807: H.1 Maximum Ratings
T = 25°C under nominal conditions unless otherwise noted. Ratings Symbol Unit VSENSE Max Rating – VSENSE_M 1. T : Junction Temperature 2. T : Ambient Temperature S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 808: H.2 Static Electrical Characteristics
VSUP VSENSE Series Resistor 10.5 k VSENSE_R Required to be placed externally at VSENSE pin. VSENSE Impedance – – k VSEN_IMP If path to ground is enabled. 1. T : Junction Temperature S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 809: H.3 Dynamic Electrical Characteristics
Ratings Symbol Unit s Enable Stabilisation Time – – EN_UNC Voltage Warning Low Pass Filter – – VWLP_filter 1. T : Junction Temperature 2. T : Ambient Temperature S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 810 Appendix H BATS Electrical Specifications S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 811: Appendix I Vreg Electrical Specifications
API start up delay Temperature Sensor Slope 5.05 5.25 5.45 Temperature Sensor Output Voltage High Temperature Interrupt Assert HTIA High Temperature Interrupt Deassert HTID Bandgap output voltage 1.13 1.22 1.32 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 812: Vreg Electrical Specifications
The LVR monitors the voltages VDD, VDDF and VDDX. If the voltage drops on these supplies to a level which could prohibit the correct function (e.g. code execution) of the microcontroller, the LVR triggers. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 813: J.1 Osclcp Electrical Characteristics
2. Needs to be measured at room temperature on the application board using a probe with very low (<=5pF) input capacitance. 3. Needs to be measured at room temperature on the application board using a probe with very low (<=5pF) input capacitance. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 814 Appendix J Electrical Characteristics for the Oscillator (OSCLCPcr) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 815: K.1 Dc Electrical Specifications
(1), (2) — 1000 4000 Crystal Start-up Time 1. This parameter is characterized before qualification rather than 100% tested. 2. Proper PC board layout procedures must be followed to achieve specifications. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 816 Appendix K OSC32K Electrical Specifications S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 817: L.1 Master Mode
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure L-1. SPI Master Timing (CPHA=0) In Figure L-2. the timing diagram for master mode with transmission format CPHA=1 is depicted. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 818 Data Valid after SS fall (CPHA=0) — — Data Hold Time (Outputs) — — Rise and Fall Time Inputs — — Rise and Fall Time Outputs — — 1. pls. see Figure L-3. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 819: S12Zvhy/S12Zvhl Family Reference Manual Rev. 1.05 Freescale Semiconductor
(= minimum Baud Rate Divisor, pls. see SPI Block Guide) derates with increasing f , please see Figure L-3.. Slave Mode In Figure L-4. the timing diagram for slave mode with transmission format CPHA=0 is depicted. S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 820 BIT 6 . . . 1 SLAVE MSB OUT SLAVE LSB OUT note (OUTPUT) MOSI MSB IN BIT 6 . . . 1 LSB IN (INPUT) NOTE: Not defined! Figure L-5. SPI Slave Timing (CPHA=1) S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 821 Data Valid after SS fall — — Data Hold Time (Outputs) — — Rise and Fall Time Inputs — — Rise and Fall Time Outputs — — 1. 0.5t added due to internal synchronization delay S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 822 Appendix L SPI Electrical Specifications S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 823: M.1 Maximum Ratings
Receiver recessive state LINrec LINSUP 0.475 0.525 LIN_CNT th_dom th_rec LIN_CNT LINSUP 0.175 th_rec th_dom LINSUP Maximum capacitance allowed on slave node including slave external components Capacitance of the LIN pin, Recessive state S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 824: M.3 Dynamic Electrical Characteristics
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/S s Rising/falling edge time (min to max / max to min) rise s Over-current masking window (IRC trimmed at 1MHz) OCLIM S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 825 Rising/falling edge time (min to max / max to min) rise s Over-current masking window (IRC trimmed at 1MHz) OCLIM 1. For 3.5V<= V <7V, the LINPHY is still working but with degraded parametrics. LINSUP S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 826 Appendix M LINPHY Electrical Specifications S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 827: Appendix N Ordering Information
9 = Flash Status / Partnumber type: S or SC = Maskset specific partnumber MC = Generic / mask-independent partnumber P or PC = prototype status (pre qualification) Figure N-1. Part Number S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 828: Appendix O
Appendix O Package Information Appendix O Package Information S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 829: O.1 144 Lqfp
Appendix O Package Information 144 LQFP S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 830 Appendix O Package Information S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 831 Appendix O Package Information S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 832: O.2 100 Lqfp
Appendix O Package Information 100 LQFP S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 833 Appendix O Package Information S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 834 Appendix O Package Information S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 835 Appendix O Package Information S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 836: P.1 Detailed Register Map
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0000 PARTID0 0x0001 PARTID1 Revision Dependent 0x0002 PARTID2 0x0003 PARTID3 0x0003 PARTID3 1. for ZVHY 2. for ZVHL S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 837: Appendix P Detailed Register Address Map
0x001E INT_CFDATA6 R RQST PRIOLVL[2:0] 0x001F INT_CFDATA7 R RQST PRIOLVL[2:0] 0x0020–0x006F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0020- Reserved 0x006F S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 838 ABCM 0x0102 DBGTCRH reserved TSOURCE TRANGE TRCMOD TALIGN 0x0103 DBGTCRL DSTAMP PDOE PROFILE STAMP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x0104 DBGTB S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 839 Bit 24 0x0119 DBGAD1 Bit 23 Bit 16 0x011A DBGAD2 Bit 15 Bit 8 0x011B DBGAD3 Bit 7 Bit 0 0x011C DBGADM0 Bit 31 Bit 24 0x011D DBGADM1 Bit 23 Bit 16 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 840 Bit 24 0x0139 DBGCD1 Bit 23 Bit 16 0x013A DBGCD2 Bit 15 Bit 8 0x013B DBGCD3 Bit 7 Bit 0 0x013C DBGCDM0 Bit 31 Bit 24 0x013D DBGCDM1 Bit 23 Bit 16 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 841 Bit 2 Bit 1 Bit 0 0x0200 MODRR0 C0RR 0x0201 MODRR1 PWM6RR PWM4RR PWM2RR PWM0RR 0x0202 MODRR2 SCI1RR IIC0RR T1IC0RR1 T1IC0RR0 0x0203 MODRR3 S0L0RR2 S0L0RR1 S0L0RR0 0x0204– Reserved 0x0207 0x0208 ECLKCTL NECLK S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 842 PERA2 PERA1 PERA0 0x0227 PERB PERB3 PERB2 PERB1 PERB0 0x0228 PPSA PPSA7 PPSA6 PPSA5 PPSA4 PPSA3 PPSA2 PPSA1 PPSA0 0x0229 PPSB PPSB3 PPSB2 PPSB1 PPSB0 0x022A– Reserved 0x023D 0x023E WOMA WOMA3 WOMA2 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 843 PTIE3 PTIE2 PTIE1 PTIE0 0x0262 PTIE PTIF7 PTIF6 PTIF5 PTIF4 PTIF3 PTIF2 PTIF1 PTIF0 0x0263 PTIF 0x0264 DDRE DDRE3 DDRE2 DDRE1 DDRE0 0x0265 DDRF DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 844 PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 PERADL2 PERADL1 PERADL0 0x0288 Reserved 0x0289 PPSADL PPSADL7 PPSADL6 PPSADL5 PPSADL4 PPSADL3 PPSADL2 PPSADL1 PPSADL0 0x028A– Reserved 0x028B 0x028C Reserved 0x028D PIEADL PIEADL7 PIEADL6 PIEADL5 PIEADL4 PIEADL3 PIEADL2 PIEADL1 PIEADL0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 845 PTS1 PTS0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 0x02D1 PTIS 0x02D2 DDRS DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0x02D3 PERS PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 846 0x0301 PTIH 0x0302 DDRH DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 0x0303 PERH PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 0x0304 PPSH PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 847 0x0351 PTIU 0x0352 DDRU DDRU7 DDRU6 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0 0x0353 PERU PERU7 PERU6 PERU5 PERU4 PERU3 PERU2 PERU1 PERU0 0x0354 PPSU PPSU7 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 848 FSTAT CCIF ACCERR FPVIOL 0x0387 FERSTAT DFDIF SFDIF RNV6 0x0388 FPROT FPOPEN FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 0x0389 DFPROT DPOPEN DPS6 DPS5 DPS4 DPS3 DPS2 DPS1 DPS0 0x038A FOPT 0x038B FRSV1 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 849 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0x0398- Reserved 0x039F 0x03A0–0x03BF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x03A0- Reserved 0x03BF S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 850 DDATA[7:0] ECCDE 0x03CE DECC[5:0] ECCDCMD 0x03CF ECCDRR ECCDW ECCDR 0x03D0–0x03FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x03D0- Reserved 0x03FF S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 851 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x0410 TIM1TCxH – – TIM1TCxL 0x041F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 852 PPOL3 PPOL2 PPOL1 PPOL0 0x0482 PWMCLK PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 0x0483 PWMPRCLK PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 0x0484 PWMCAE CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 853 0x0492 PWMCNT6 Bit 7 Bit 0 0x0493 PWMCNT7 0x0494 PWMPER0 Bit 7 Bit 0 0x0495 PWMPER1 Bit 7 Bit 0 0x0496 PWMPER2 Bit 7 Bit 0 0x0497 PWMPER3 Bit 7 Bit 0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 854 0x05C0–0x05EF Timer Module (TIM0) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x05C0 TIM0TIOS IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 855 TIM0TCxH – – TIM0TCxL 0x05DF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x05E0 TIM0PACTL PAEN PAMOD PEDGE CLK1 CLK0 PAOVI 0x05E1 TIM0PAFLG PAOVF PAIF S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 856 CSL_BMOD RVL_BMOD SMOD_ACC AUT_RSTA DBECC_ER Reserved READY 0x0602 ADC0STS CSL_SEL RVL_SEL 0x0603 ADC0TIM PRS[6:0] 0x0604 ADC0FMT SRES[2:0] LDOK 0x0605 ADC0FLWCTL SEQA TRIG RSTA 0x0606 ADC0EIE IA_EIE CMD_EIE EOL_EIE TRIG_EIE RSTAR_EIE LDOK_EIE Reserved S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 857 ADC0EOLRI 0x0611 Reserved 0x0612 Reserved R Reserved Reserved 0x0613 Reserved CMD_SEL INTFLG_SEL[3:0] 0x0614 ADC0CMD_0 R VRH_SEL VRL_SEL CH_SEL[5:0] 0x0615 ADC0CMD_1 SMP[4:0] Reserved 0x0616 ADC0CMD_2 0x0617 ADC0CMD_3 Reserved Reserved Reserved 0x0618 Reserved Reserved S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 858 RES_IDX[5:0] 0x0620 ADC0RIDX RES_PTR[19:16] 0x0621 ADC0RBP_0 0x0622 ADC0RBP_1 RES_PTR[15:8] 0x0623 ADC0RBP_2 RES_PTR[7:2] CMDRES_OFF0[6:0] 0x0624 ADC0CROFF0 ADC0CROFF1 0x0625 CMDRES_OFF1[6:0] 0x0626 Reserved Reserved 0x0627 Reserved Reserved 0x0628 Reserved Reserved R Reserved Reserved 0x0629 Reserved S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 859 CPMUINT RTIE LOCKIE OSCIE 0x06C9 CPMUCLKS PLLSEL PSTP CSAD OSCSEL1 OSCSEL OSCSEL0 0x06CA CPMUPLL 0x06CB CPMURTI RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 0x06CC CPMUCOP WCOP RSBCK WRTMAS RESERVED 0x06CD CPMUTEST0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 860 HTTR0 CPMU 0x06D8 TCTRIM[4:0] IRCTRIM[9:8] IRCTRIMH CPMU 0x06D9 IRCTRIM[7:0] IRCTRIML 0x06DA CPMUOSC OSCE Reserved 0x06DB CPMUPROT PROT RESERVED 0x06DC CPMUTEST2 CPMU 0x06DD EXTXON INTXON VREGCTL 0x06DE CPMUOSC2 OMRE OSCMOD CPMU 0x06DF RESERVED1F S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 861 SBR12 SBR11 SBR10 SBR9 SBR8 0x0701 SCI0BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x0702 SCI0CR1 LOOPS SCISWAI RSRC WAKE 0x0700 SCI0ASR1 RXEDGIF BERRV BERRIF BKDIF 0x0701 SCI0ACR1 RXEDGIE BERRIE BKDIE S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 862 SBR2 SBR1 SBR0 0x0712 SCI1CR1 LOOPS SCISWAI RSRC WAKE 0x0710 SCI1ASR1 RXEDGIF BERRV BERRIF BKDIF 0x0711 SCI1ACR1 RXEDGIE BERRIE BKDIE 0x0712 SCI1ACR2 IREN TNP1 TNP0 BERRM1 BERRM0 BKDFE 0x0713 SCI1CR2 TCIE ILIE S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 863 MSTR CPOL CPHA SSOE LSBFE 0x0781 SPI0CR2 XFRW MODFEN BIDIROE SPISWAI SPC0 0x0782 SPI0BR SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIF SPTEF MODF 0x0783 SPI0SR 0x0784 SPI0DRH 0x0785 SPI0DRL 0x0786- Reserved 0x0787 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 864 GCEN ADTYPE ADR10 ADR9 ADR8 0x07C6 Reserved 0x07C7 Reserved 0x07C8–0x07FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x07C8- Reserved 0x07FF S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 865 IDAM1 IDAM0 0x080C Reserved 0x080D CAN0MISC BOHOLD R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 0x080E CAN0RXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0x080F CAN0TXERR 0x0810- CAN0IDAR0–3 0x0813 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 866 Reserved Reserved Reserved Reserved Reserved Reserved 0x0983 LP0SLRM LPDTDIS LPSLR1 LPSLR0 0x0984 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LPDT 0x0985 LP0SR 0x0986 LP0IE LPDTIE LPOCIE 0x0987 LP0IF LPDTIF LPOCIF S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 867 FP4BP1 FP4BP0 0x0A0B LCDRAM3 FP7BP3 FP7BP2 FP7BP1 FP7BP0 FP6BP3 FP6BP2 FP6BP1 FP6BP0 0x0A0C LCDRAM4 FP9BP3 FP9BP2 FP9BP1 FP9BP0 FP8BP3 FP8BP2 FP8BP1 FP8BP0 0x0A0D LCDRAM5 FP11BP3 FP11BP2 FP11BP1 FP11BP0 FP10BP3 FP10BP2 FP10BP1 FP10BP0 S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 868 FP39BP1 FP39BP0 FP38BP3 FP38BP2 FP38BP1 FP38BP0 0x0A1C- Reserved 0x0A1F 0x0A20–0x0A3F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0A20- Reserved 0x0A3F S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 869 MCOM0 MCAM1 MCAM0 0x0A52 MCCC2 MCOM1 MCOM0 MCAM1 MCAM0 0x0A53 MCCC3 MCOM1 MCOM0 MCAM1 MCAM0 0x0A54– Reserved 0x0A5F 0x0A60 MCDC0H 0x0A61 MCDC0L 0x0A62 MCDC1H 0x0A63 MCDC1L 0x0A64 MCDC2H 0x0A65 MCDC2L 0x0A66 MCDC3H S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 870 0x0A90–0x0A97 Stepper Stall Detector (SSD1) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0A90 RTZ1CTL DCOIL RCIR STEP 0x0A91 MDC1CTL MCZIE MODMC RDMCL MCEN AOVIE FLMC S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 871 RTCPS3 RTCPS2 RTCPS1 RTCPS0 0x0AE2 RTCCTL3 CALS W RTCWE1 RTCWE0 RTCCTL4 0x0AE3 HRIE MINIE SECIE COMPIE TB0IE CDLC 0x0AE4 RTCS1 MINF SECF COMPF TB0F RTCCCR 0x0AE5 0x0AE6 RTCMODH RTCMODH RTCMODL 0x0AE7 RTCMODL S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 872 SSG0PSH 0x0B03 SSG0PSL TONE9 TONE8 0x0B04 SSG0TONEH 0x0B05 TONE7 TONE6 TONE5 TONE4 TONE3 TONE2 TONE1 TONE0 SSG0TONEL 0x0B06 AMP10 AMP9 AMP8 SSG0AMPH 0x0B07 AMP7 AMP6 AMP5 AMP4 AMP3 AMP2 AMP1 AMP0 SSG0AMPL S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 873 DCNT3 DCNT2 DCNT1 DCNT0 0x0B12 SSG0DCNT 0x0B13- RESERVED 0x0B17 0x0B18–0x0FFF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0B18- Reserved 0x0FFF S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05 Freescale Semiconductor...
Page 874 Freescale, the Freescale logo and MagniV are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. , All other product or service names are the property of their respective owners. © 2015 Freescale Semiconductor, Inc. MC9S12ZVHYRMV1 Rev. 1.05...

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Freescale Semiconductor MC9S12ZVHL64 Reference Manual

Device Overview Mc9S12Zvhy/Mc9S12Zvhl Families

Chapter 1

Chapter 10

Chapter 23

Chapter 2

Chapter 5

Chapter 4

Chapter 22

Table of Contents

Chapter 6

Chapter 7

Chapter 8

Chapter 9 PWM Channel Timers

10.4 Memory Map and Register Definition

Chapter 12

Chapter 16

Chapter 13

Chapter 14

Chapter 15

Chapter 17

Chapter 18

Chapter 19

Chapter 20

Chapter 21 64 KB Flash Module (S12ZFTMRZ64K2KV2)

Appendix A

Appendix B

Appendix D IRC Electrical Specifications

Appendix C Appendix D

Appendix E

Appendix F

Appendix G

Appendix H

Appendix I VREG Electrical Specifications

Appendix J

Appendix K

Appendix L

Appendix M

Appendix N Ordering Information

Appendix O

Appendix P Detailed Register Address Map

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