Teknor Industrial Computers VIPer 821 Technical Reference Manual page 55

Option BIOS
Default
Peer Concurrency En.
Chipset Special En.
Features
DRAM ECC/PARITY Parity
Select
Memory Parity/ECC Auto
Check
Single Bit Error Report En.
Chipset NA# Asserted En.
Pipeline Cache Timing Faster
Passive Release En.
Delayed Transaction Dis.
Memory Hole Location None
Supervisor I/O Base 190h
Addr.
Setup Possible
Default Settings
En. En., Dis. Peer concurrency means that more than one PCI device can be
active at a time.
En. En., Dis. When Disabled, the chipset behaves as if it were the earlier Intel
82430FX chipset.
Parity ECC, Parity Set this option according to the type of DRAM installed in your
system: error-correcting code (ECC) or parity (default).
Auto En., Dis., Auto In Auto mode, the BIOS enables memory checking automatically
when it detects the presence of ECC or parity DRAM.
En. En., Dis. If ECC is enabled, selecting Enabled here tells the system to
report an error when a correctable single-bit error occurs.
En. En., Dis. When Enabled, the chipset will use the NA (Next Address)
protocol with the CPU to enable cache bursting.
Faster Faster, For a secondary cache of 256KB (one bank), select Faster. For a
secondary cache of 512KB (two banks), the system designer must
Fastest
select Faster (3-1-1-1, 2-1-1-1) or Fastest (3-1-1-1, 1-1-1-1).
Cache timing 3-1-1-1 is at the CPU access speed. It requires
special SRAMs because the 3-1-1-1 timing is at the CPU clock
rate.
En. En., Dis. When Enabled, CPU to PCI bus accesses are allowed during
passive release otherwise the arbiter only accepts another PCI
master access to local DRAM.
The chipset has an embedded 32-bit posted write buffer to
En. En., Dis.
support delay transactions cycles. Select Enabled to support
compliance with PCI specifications version 2.1.
None 512K-640K, You can reserve this area of system memory for ISA adapter
15M-16M, ROM. When this area is reserved, it cannot be cached. The user
None information of peripherals that need to use this area of system
memory usually discusses their memory requirements.
190h 190h, 290h, This option determines the base address for the Supervisor I/O
390h Register.
4-7
BIOS Setup Program
Description