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Schematic Diagrams
PCH 1/9
CONSENT STRAP
ENABLE:LOW
SPI_IO2
SPI_IO3
PESONALITY STRAP
D
ENABLE:LOW
BOOT HALT
ENABLE:LOW
(INTERNAL WEAK PU)
SPI_SI_R
SPI_SO_R
Sheet 35 of 91
JTAG ODT
DISABLE:LOW
(INTERNAL WEAK PU)
PCH 1/9
BIOS ROM 128MB
D01A 0829
Change power plane
SPI_3.3V
C
B
20180509 Follow common design modify CNVi circuit
CNVI_BRI_RSP
CNVI_RGI_RSP
D02 0921
GPP_J1
VCCPSPI VOLTAGE SELECT
LOW: 3.3V (DEFAULT)
HIGH: 1.8V
(INTERNAL WEAK PD)
A
B - 36 PCH 1/9
5
4
Pin Straps(2)
ESPI FLASH SHARING MODE
LOW: MASTER ATTACHED FLASH SHARING (MAFS)
R794
*4.7K_04
HIGH: SLAVE ATTACEHD FLASH SHARING (SAFS)
(INTERNAL WEAK PD)
R793
*1K_04
GPP_H12
R389
*20K_04
3.3VA
20180727 ADD SPI TPM
RESERVED
External pull-up is required. Recommend
100K if pulled up to 3.3V or 75K if
pulled up to 1.8V.
D01A 0829
This strap should sample HIGH. There
Modify pwr plane
should NOT be any on-board device
driving it to opposite direction during
SPI_3.3V
strap sampling.
R347
*100K_04
GPP_H15
R379
20K_04
R333
*4.7K_04
R383
*100K_04
3.3VA
20180727
Change stuff location
R317
*4.7K_04
W/O TPM
R852
0_04
VDD3
W/O TPM
SPI_* = 1"~6.5"
W/ TPM
R853
0_04
3.3VA
U61
W/ TPM
8
5
SPI_SI_M
SPI_SI_R
R823
33_04
VDD
SI
SPI_SO_M
SPI_SO_R
C1554
R818
2
R812
33_04
SO
20K_04
SPI_W P#
SPI_CS0#
SPI_CS_0#
3
1
R811
0_04
WP#
CE#
SPI_SCLK_M
SPI_SCLK_R
R813
6
R819
33_04
SCK
20K_04
SPI_HOLD#
7
4
HOLD#
VSS
MX25L12873F
128Mbit / 3.3V
MXIC P/N = 6-04-25128-A72
20180521 RF check
close to PCH
R215
20K_04
+V3.3A_V1.8A_VCCPGPPD
R201
20K_04
+V3.3A_V1.8A_VCCPGPPD
20180806
GPP_J5 : INTERNAL PU 20K
PCH use internal LDO
GPP_J7 : INTERNAL PU 20K
R868
10K_04
+V3.3A_V1.8A_VCCPGPPD
CNVI_MFUART2_TXD
5
4
3
U30A
GPP_A11
BE36
T90
GPP_A11/PME#/SD_VDD2_PWR_EN#
GPP_B13/PLTRST#
R15
RSVD2
R13
GPP_K16/GSXCLK
RSVD1
GPP_K12/GSXDOUT
GPP_K13/GSXSLOAD
GPP_K14/GSXDIN
AL37
GPP_K15/GSXSRESET#
VSS_AL37
AN35
TP
D02 1005
SPI_SI_R
5.1Ω
to 0Ω
R334
0_04
AU41
GPP_E3/CPU_GP0
SPI0_MOSI
SPI_SO_R
R316
0_04
BA45
GPP_E7/CPU_GP1
SPI0_MISO
SPI_CS_0#
AY47
GPP_B3/CPU_GP2
SPI0_CS0#
SPI_SCLK_R
AW47
R360
0_04
GPP_B4/CPU_GP3
SPI0_CLK
AW48
SPI0_CS1#
GPP_H18/SML4ALERT#
SPI_W P#
SPI_IO2
R381
33_04
AY48
SPI0_IO2
GPP_H17/SML4DATA
SPI_HOLD#
33_04
SPI_IO3
R382
BA46
SPI0_IO3
GPP_H16/SML4CLK
AT40
R362
*20K_04
SPI0_CS2#
GPP_H15/SML3ALERT#
SPI_3.3V
R361
*20K_04
BE19
GPP_H14/SML3DATA
D01A 0829
GPP_D1/SPI1_CLK/SBK1/BK1
BF19
GPP_H13/SML3CLK
Modify pwr plane
GPP_D0/SPI1_CS#/SBK0/BK0
BF18
GPP_H12/SML2ALERT#
GPP_D3/SPI1_MOSI/SBK3/BK3
BE18
GPP_H11/SML2DATA
GPP_D2/SPI1_MISO/SBK2/BK2
BC17
GPP_H10/SML2CLK
GPP_D22/SPI1_IO3
BD17
52
SPI_CS_2#
GPP_D21/SPI1_IO2
20180727 ADD SPI TPM
1 OF 13
HM370_MP
W/ TPM
D02 1005 Add
R881
0_04
TPM_SPI_SI_R
52
W/ TPM
R882
0_04
TPM_SPI_SO_R
52
W/ TPM
EDP
R883
0_04
TPM_SPI_SCLK_R
52
GSYNC
W/ TPM
D01A 0828
Add
R848
0_04
EC_SPI_SI_R
55
W/O TPM
R849
0_04
EC_SPI_SO_R
55
W/O TPM
R850
0_04
EC_SPI_CS_0#
55
W/O TPM
R851
0_04
EC_SPI_SCLK_R
55
W/O TPM
U30M
W/O TPM
GSYNC_DET
AW13
GPP_G0/SD_CMD
GPP_G1
BE9
GPP_G1/SD_DATA0
NVSR_DET#
BF8
10
NVSR_DET#
GPP_G2/SD_DATA1
BF9
GPP_G3/SD_DATA2
BG8
GPP_G4/SD_DATA3
BE8
20180430 GPP_G5 Del PS8338B_SW
GPP_G5/SD_CD#
BD8
37
SW I#_GPP_G6
GPP_G6/SD_CLK
AV13
GPP_G7/SD_WP
AP3
GPP_I11/M2_SKT2_CFG0
AP2
44
SATA_PW R_EN
GPP_I12/M2_SKT2_CFG1
AN4
GPP_I13/M2_SKT2_CFG2
20180424 Add to Control HDD RTD3
AM7
GPP_I14/M2_SKT2_CFG3
AV6
45
CNVI_GNSS_PA_BLANKING
GPP_J0/CNV_PA_BLANKING
GPP_J1
AY3
65,70
GPP_J1
GPP_J1/CPU_C10_GATE#
AR13
GPP_J11/A4WP_PRESENT
AV7
To M.2
GPP_J10
AW3
GPP_J2
Zo=50ohm, L<10"
close to PCH
AT10
GPP_J3
CNVI_BRI_DT_R
R198
33_04
AV4
45
CNVI_BRI_DT
GPP_J4/CNV_BRI_DT/UART0B_RTS#
AY2
45
CNVI_BRI_RSP
CNVI_RGI_DT_R
GPP_J5/CNV_BRI_RSP/UART0B_RXD
R214
33_04
BA4
45
CNVI_RGI_DT
GPP_J6/CNV_RGI_DT/UART0B_TXD
AV3
45
CNVI_RGI_RSP
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
AW2
45
CNVI_MFUART2_RXD
GPP_J8/CNV_MFUART2_RXD
CNVI_MFUART2_TXD
AU9
45
CNVI_MFUART2_TXD
GPP_J9/CNV_MFUART2_TXD
HM370_MP
4,10,29,31,34,36,37,38,41,43,45,46,52,53,55,57,58,64,65,66,67,68,69,71,72,74,77,78
41,45
+V3.3A_V1.8A_VCCPGPPD
4,29,34,37,38,41,43,52,64,65,68,69
8,9,10,11,12,13,14,29,34,37,38,39,40,43,44,46,47,53,54,55,56,57,60,63,64,70,71,77
3
2
1
AV29
PLT_RST#
34,43
R331
*10K_04
Y47
3.3VS
20180720 Add
Y46
PCH_GPP_K12
56
Y48
W46
GPP_K14_TEST_R
51
20180720 Add ANX7411 Interrupt
AA45
GPP_K15_INTP_OUT
51
20180717 Add ANX7411 Interrupt
AL47
AM45
R731
10K_04
3.3VS
BF32
PCH_GPP_B3
56
BC33
AE44
D02A Del SD40 RTD3 function
AJ46
TBT_FORCE_PW R_R
59
AE43
TBT_RTD3_PW R_EN_R
59
AC47
GPP_H15
TBTA_MRESET
AD48
T98
20180613 modify 65987, delete TBTA_MRESET
AF47
TBTA_HRESET
61
GPP_H12
AB47
AD47
AE48
BB44
R315
1M_04
INTRUDER#
VCC_RTC
D02 0926
BIOS setting
NVSR_DET# H : W/O NVSR Panel
3.3VS
20180806
L : W/ NVSR Panel
unstuff
GSYNC_DET NVSR_DET
NVSR_DET#
R674
*10K_04
L
H
GSYNC_DET H : W/ GSYNC
H
H
L : W/O GSYNC
GSYNC_DET
R236
10K_04
W / GSYNC
R235
10K_04
W /O GSYNC
To M.2
DIFF=85ohm, L<10"
BD4
CNVI_W R_CLKN
CNV_WR_CLKN
BE3
CNV_WR_CLKP
CNVI_W R_CLKP
BB3
CNV_WR_D0N
CNVI_W R_D0N
BB4
CNVI_W R_D0P
CNV_WR_D0P
BA3
CNV_WR_D1N
CNVI_W R_D1N
BA2
CNV_WR_D1P
CNVI_W R_D1P
BC5
CNVI_W T_CLKN
CNV_WT_CLKN
BB6
CNVI_W T_CLKP
CNV_WT_CLKP
BE6
CNV_WT_D0N
CNVI_W T_D0N
BD7
CNV_WT_D0P
CNVI_W T_D0P
BG6
CNVI_W T_D1N
CNV_WT_D1N
BF6
CNV_WT_D1P
CNVI_W T_D1P
BA1
CNV_WT_RCOMP
R659
150_1%_04
B12
PCIECOMP_N
R691
100_1%_04
PCIE_RCOMPN
PCIECOMP_P
A13
PCIE_RCOMPP
SD_RCOMP_1P8
BE5
R204
200_1%_04
SD_1P8_RCOMP
SD_RCOMP_3P3
BE4
R205
200_1%_04
SD_3P3_RCOMP
BD1
GPPJ_RCOMP_1P81
BE1
GPPJ_RCOMP_1P82
GPPJ_RCOMP_1P8
BE2
R669
200_1%_04
GPPJ_RCOMP_1P83
Y35
RSVD2
Y36
RSVD3
BC1
RSVD1
AL35
TP
13 OF 13
VDD3
Title
Title
Title
41
SPI_3.3V
07-01-1 PCH A,M/13-SPI/SMB/CNVI
07-01-1 PCH A,M/13-SPI/SMB/CNVI
07-01-1 PCH A,M/13-SPI/SMB/CNVI
3.3VA
3.3VS
Size
Size
Size
Document Number
Document Number
Document Number
6-71-PB500-D03
6-71-PB500-D03
6-71-PB500-D03
38,41
VCC_RTC
A3
A3
A3
PB50EF
PB50EF
PB50EF
Date:
Date:
Date:
Friday, December 07, 2018
Friday, December 07, 2018
Friday, December 07, 2018
Sheet
Sheet
Sheet
35
35
35
o f
o f
o f
2
1
D
C
45
45
45
45
45
45
45
45
45
B
45
45
45
A
R e v
R e v
R e v
D03
D03
D03
91
91
91
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