Table of Contents
Advertisement
Frame Buffer Partition C
5
FRAME BUFFER PARTITION C 31..0
VRAM=K4Z80325BC-HC14
M5A
NORMAL
FBC_D1
B4
DQ0_A
FBC_D7
A3
DQ1_A
FBC_D5
B3
DQ2_A
FBC_D4
20180719
B2
D
DQ3_A
Modify the order
FBC_D6
E3
DQ4_A
FBC_D3
E2
DQ5_A
FBC_D0
F2
DQ6_A
FBC_D2
G2
DQ7_A
FBC_EDC0
C2
EDC0_A
FBC_DBI0
D2
DBI0_A
FBC_W CK01
D4
WCK0_t_A
FBC_W CK01*
D5
WCK0_c_A
x16
x8
FBC_D14
B11
NC
DQ8_A
FBC_D15
A12
NC
DQ9_A
FBC_D8
B12
DQ10_A
NC
FBC_D12
B13
NC
DQ11_A
FBC_D13
E12
NC
DQ12_A
FBC_D9
E13
NC
DQ13_A
FBC_D11
F13
DQ14_A
NC
FBC_D10
G13
DQ15_A
NC
FBC_EDC1
C13
EDC1_A
GND
FBC_DBI1
D13
DBI1_A
NC
FBC_W CKB01
D11
WCK1_t_A
NC
FBC_W CKB01*
D10
WCK1_c_A
NC
C
K4Z80325BC-HC14
P/N =
Close to DRAM
Close to DRAM
FBVDDQ
FBVDDQ
C859
C814
C817
C815
C828
C664
Around DRAM
Around DRAM
FBVDDQ
FBVDDQ
C532
C925
C829
C839
C878
C877
B
FBVDDQ
FBVDDQ
Right under DRAM
Right under DRAM
C1353
C853
C1354
C864
C821
C1352
C837
C844
C1367
C867
FBVDDQ
FBVDDQ
Close to DRAM
Close to DRAM
A
C852
C847
C857
C866
C862
C836
C846
C827
C834
C865
5
4
3
21
FBC_W CK01
21
FBC_W CK01*
21
FBC_W CK23
21
FBC_W CK23*
M5B
21
FBC_W CKB01
NORMAL
21
FBC_W CKB01*
21
FBC_W CKB23
x16
x8
21
FBC_W CKB23*
FBC_D25
U4
DQ0_B
NC
FBC_D29
V3
DQ1_B
NC
FBC_D28
U3
DQ2_B
NC
FBC_D31
U2
DQ3_B
NC
FBC_D26
P3
DQ4_B
NC
FBC_CMD0
H3
FBC_D24
P2
FBC_CMD9
DQ5_B
NC
G11
FBC_D30
N2
DQ6_B
NC
FBC_CMD8
G4
FBC_D27
M2
DQ7_B
NC
FBC_CMD32
H12
FBC_CMD7
H5
FBC_EDC3
T2
EDC0_B
GND
FBC_CMD11
H10
FBC_DBI3
R2
DBI0_B
FBC_CMD15
NC
J12
FBC_CMD14
J11
FBC_W CKB23
R4
WCK0_t_B
NC
FBC_CMD3
J4
FBC_W CKB23*
R5
WCK0_c_B
NC
FBC_CMD1
J3
FBC_CMD6
J5
FBC_D23
U11
DQ8_B
FBC_CMD10
G10
FBC_D20
V12
DQ9_B
FBC_D22
U12
DQ10_B
FBC_D21
U13
DQ11_B
FBC_D18
P12
DQ12_B
FBC_D19
P13
DQ13_B
FBC_D17
N13
DQ14_B
FBC_D16
M13
DQ15_B
FBC_CMD4
L3
FBC_EDC2
T13
EDC1_B
FBC_CMD12
M11
FBC_DBI2
R13
DBI1_B
FBC_CMD5
M4
FBC_CMD13
L12
FBC_W CK23
R11
FBC_CMD7
WCK1_t_B
L5
FBC_W CK23*
R10
WCK1_c_B
FBC_CMD11
L10
FBC_CMD15
K12
FBC_CMD14
K11
FBC_CMD3
K4
K4Z80325BC-HC14
FBC_CMD1
K3
P/N =
FBC_CMD6
K5
FBC_CMD10
M10
FBC_CMD2
J1
K10
21
FBC_CLK0*
J10
21
FBC_CLK0
OPTION, Under DRAM
1V8_AON
C854
C848
C831
C851
C832
C849
C819
20180802 0.47u_4V_X6S_02 to 0.47u_6.3V_X5R_04
FBVDDQ
FBVDDQ
C1366
C820
C826
C838
C843
C833
C825
C842
C1368
C869
C868
4
3
2
FBC_W CK01
FBC_DBI[3..0]
M5D
FBC_W CK01*
21
FBC_DBI[3..0]
FBC_W CK23
FBC_EDC[3..0]
FBC_W CK23*
21
FBC_EDC[3..0]
FBC_CMD[15..0]
FBC_W CKB01
21
FBC_CMD[15..0]
FBC_W CKB01*
FBC_CMD32
A11
21
FBC_CMD32
VSS
FBC_W CKB23
A13
FBC_D[31..0]
VSS
FBC_W CKB23*
21
FBC_D[31..0]
A2
VSS
A4
VSS
B1
M5C
VSS
B14
VSS
C10
VSS
C12
VSS
K1
FBC_VREFC
C3
CA0_A
VREFC
VSS
C5
CA1_A
VSS
D1
CA2_A
VSS
D12
CA3_A
VSS
D14
CA4_A
VSS
D3
CA5_A
VSS
E11
CA6_A
VSS
E4
CA7_A
VSS
F1
CA8_A
VSS
F12
CA9_A
VSS
F14
CABI_A
VSS
F3
CKE_A
VSS
G1
VSS
N5
G12
TCK
VSS
F10
G14
TDI
VSS
N10
20180809 Del test point
G3
TDO
VSS
F5
H11
TMS
VSS
H4
VSS
L11
VSS
L4
CA0_B
VSS
M1
CA1_B
VSS
M12
CA2_B
VSS
M14
CA3_B
VSS
M3
CA4_B
VSS
N1
CA5_B
VSS
N12
CA6_B
VSS
N14
CA7_B
VSS
N3
CA8_B
VSS
P11
CA9_B
VSS
P4
CABI_B
VSS
R1
CKE_B
VSS
J14
FBC_ZQ_1_A
R12
ZQ_A
VSS
FBC_ZQ_1_B
K14
R14
ZQ_B
VSS
R3
VSS
T10
VSS
T12
R155
R589
VSS
T3
RESET
VSS
121_1%_04
121_1%_04
T5
VSS
U1
VSS
U14
VSS
V11
CLK_c
VSS
V13
CLK_t
VSS
V2
VSS
V4
VSS
G5
RFU_A
M5
20180809 Del test point
RFU_B
K4Z80325BC-HC14
K4Z80325BC-HC14
P/N =
P/N =
FBVDDQ
R114
*549_1%_04
R113
1K_1%_04
G
17,19,24,29
GPIO10_FBVREF_SEL
17,18,19,20,23,24,25,26,29,30,31,32,34,66,74,77
16,17,18,19,20,21,23,24,25,30,32,77
C824
C822
C823
Title
Title
Title
Size
Size
Size
Document Number
Document Number
Document Number
6-71-PB500-D03
6-71-PB500-D03
6-71-PB500-D03
A3
A3
A3
PB50EF
PB50EF
PB50EF
Date:
Date:
Date:
Thursday, January 31, 2019
Thursday, January 31, 2019
Thursday, January 31, 2019
2
Schematic Diagrams
1
FBVDDQ
A1
VDD
A14
VDD
E10
VDD
E5
VDD
H13
VDD
H2
VDD
D
L13
VDD
L2
VDD
P10
VDD
P5
VDD
V1
VDD
V14
VDD
FBVDDQ
B10
VDDQ
B5
VDDQ
C1
VDDQ
C11
VDDQ
C14
VDDQ
C4
VDDQ
E1
VDDQ
E14
VDDQ
F11
VDDQ
Sheet 22 of 91
F4
VDDQ
H1
VDDQ
H14
VDDQ
J13
VDDQ
Frame Buffer
J2
VDDQ
K13
VDDQ
K2
VDDQ
L1
VDDQ
Partition C
C
L14
VDDQ
N11
VDDQ
N4
VDDQ
P1
VDDQ
P14
VDDQ
T1
VDDQ
T11
VDDQ
T14
VDDQ
T4
VDDQ
U10
VDDQ
U5
VDDQ
1V8_AON
A10
VPP
A5
VPP
V10
VPP
V5
VPP
B
20180712 follow N18E circuit no mount
FBC_VREFC
FBC_VREFC
23
R117
C876
*931_1%_04
*820p_50V_X7R_04
Q14
*MTN2002ZS3
A
1V8_AON
FBVDDQ
[22] FBC[31..0]
[22] FBC[31..0]
[22] FBC[31..0]
R e v
R e v
R e v
D03
D03
D03
Sheet
Sheet
Sheet
22
22
22
o f
o f
o f
91
91
91
1
Frame Buffer Partition C B - 23
Hide quick links:
Advertisement
Table of Contents
