Ps8330B - Clevo PB70RC-G Service Manual

Schematic Diagrams

PS8330B

D
Sheet 13 of 91
PS8330B
C
B
DESIGN NOTE:PEQ
Programmalbe input equalization levels;internal pull
down at~150k ,3.3v I/O
L: default, LEQ, compensate channel loss up to 12dB at
HBR2
H: HEQ, compensate channel loss up to 15dB at HBR2
M:LLEQ, compensate channel loss up to 5dB at HBR2
DESIGN NOTE:CFG0
Configuration pin for automatic EQ and
Aux interception; Internal pull down at
~150Kohm,3.3V I/O
L: default, automatic EQ enable and Aux interception enable
H: automatic EQ disable and AUX interception enable
M: automatic EQ disable and AUX interception
A
disable,no pre-emphasis, 600mVpp swing
DESIGN NOTE:CFG1
Configuration pin for auto test and input offset
cancellation,3.3V IO, internal pull up at~150K
H: default, auto test disable and input offset cancellation
enable
L: auto test enable and input offset cancellation enable
M: auto test disable and input offset cancellation disable
B - 14 PS8330B
5 4
3.3VS
20180420
Del co-lay circuit
From NV Port_A
C1032 C1106
MLCC Comm part DIFF=90ohm, Total L<6"
0.1u_6.3V_X5R_02 0.01u_16V_X7R_04 C1035
27 MDP_A_AUX#_SDA
TBT TBT C1034
27 MDP_A_AUX_SCL
20180430 Del PS8338B
D02 1012
use non-dongle Cable, TBT no display
R892
R893
R273 10K_04
3.3VS
3.3VS
R722 *4.7K_04 TBT
PS8330B_CFG1
R727 *4.7K_04 TBT
From NV Port_A
close PS8330B
DIFF=90ohm, Total L<6"
C1049 0.1u_10V_X7R_04 TBT
27 MDP_A0
C1054 0.1u_10V_X7R_04 TBT
27 MDP_A#0
C1059 0.1u_10V_X7R_04 TBT
27 MDP_A1
C1067 0.1u_10V_X7R_04 TBT
27 MDP_A#1
C1072 0.1u_10V_X7R_04 TBT
27 MDP_A2
C1083 0.1u_10V_X7R_04 TBT
27 MDP_A#2
C1090 0.1u_10V_X7R_04 TBT
27 MDP_A3
C1094 0.1u_10V_X7R_04 TBT
27 MDP_A#3
20180430 Del PS8338B
20180420
Del co-lay circuit
C1105
3.3VS
R321 *4.7K_04
R322 *4.7K_04
R320 *4.7K_04
R323 *4.7K_04
R324
To NV Port_A
5 4
3
mDP REDRIVER
3.3VS
R275
PS8330B_AUXn
0.1u_10V_X7R_04 TBT 100K_04
0.1u_10V_X7R_04 TBT PS8330B_AUXp TBT
0_04 TBT
0_04 TBT
TBT R274
100K_04
3.3VS 3.3VS 3.3VS TBT
C1033
2.2u_6.3V_X5R_04
TBT
U19
PDB PIN:
L:Chip power down
H:Normal operation(default)
37 24
NC GND
IN0P_R
38 23
IN0p OUT0p
IN0N_R
39 22
IN0n OUT0n
40 21
CFG1 NC
IN1P_R
41 20
IN1p OUT1p
IN1N_R 42 19
IN1n OUT1n
PS8330B
43 18
NC GND
IN2P_R 44 17
IN2p OOUT2p
IN2N_R
45 16
IN2n OUT2n
46 15
NC NC
IN3P_R
47 14
IN3p OUT3p
IN3N_R 48 13
IN3n OUT3n
49
EPAD
PS8330B
TBT
3.3VS
2.2u_6.3V_X5R_04 CEXT
TBT
PS8330B_PEQ
TBT
PS8330B_CFG0
TBT
PS8330B_HPD
TBT R325
From TBT
TBT 1M_04
TBT
PS8330_REXT
4.99K_1%_04 TBT
34,39 MDP_A_TBT_HPD
20180430 Del PS8338B
3
2 1
20180420
Del co-lay circuit
To TBT
DIFF=100ohm, L<2"
PS8330B_AUXn_SDA 59
PS8330B_AUXp_SCL 59
To TBT
DIFF=100ohm, L<2"
PS8330B_D0P 59
PS8330B_D0N 59
20180413 del resistors
co-lay with IC pin
PS8330B_D1P 59
PS8330B_D1N 59
PS8330B_D2P 59
PS8330B_D2N 59
PS8330B_D3P 59
PS8330B_D3N 59
20180420
Del co-lay circuit
59
8,9,10,11,12,14,29,34,35,37,38,39,40,43,44,46,47,53,54,55,56,57,60,63,64,70,71,77 3.3VS
Title Title Title
[13] 04-4-2 DP REPEATER PS8330B [13] 04-4-2 DP REPEATER PS8330B [13] 04-4-2 DP REPEATER PS8330B
Size Size Size Document Number Document Number Document Number
6-71-PB500-D03 6-71-PB500-D03 6-71-PB500-D03
A3 A3 A3 PB50EF PB50EF PB50EF
Date: Date: Date: Friday, December 07, 2018 Friday, December 07, 2018 Friday, December 07, 2018 Sheet Sheet Sheet 13 13 13 o f o f o f
2 1
D
C
B
A
R e v R e v R e v
D03 D03 D03
91 91 91