Table of Contents
Advertisement
PS/2 M
(IRQ12)
OUSE
Default: Enabled
When disabled, IRQ12 is freed for other devices.
LPT1 (0378
)
H
Default: IRQ7
Allows you to disable or specify the IRQ used by LPT1 on the SMSC FDC37B727 Super I/O.
When disabled, the IRQ and I/O space are freed.
P
P
ARALLEL
ORT
Default: SPP
This option allows the user to change the communication mode of the parallel port. The options
are: SPP, SPP/EPP1.9, ECP, ECP/EPP1.9, Printer, SPP/EPP1.7, ECP/EPP1.7, and FDD. The
FDD option must be set if a floppy drive is used.
CPU S
PEED
Default: 133 MHz
The maximum clock rate for the ÉlanSC520 Microcontroller is 133 MHz. It can optionally be set
to 100 MHz for a slight power savings. If an extended temperature board version is detected, the
default will change to 100 MHz.
C
M
ACHE
ODE
Default: Write-Back
The 16 kb L1 cache can be configured for either write-through or write-back mode. This option
controls the CACHE_WR_MODE in the CPUCTL register (MMCR offset 02h).
W
B
RITE
UFFER
Default: Enabled
When the write buffer is enabled, it buffers all write activity from the CPU, PCI bus, or GP bus.
This option controls the WB_ENB bit in the DBCTL register (MMCR offset 40h).
GP B
T
US
IMINGS
Default: Normal
The GP (ISA) bus timings may need to be slowed to accommodate ISA Plug-n-Play cards. This
option modifies registers in the GP Bus Controller, MMCR offsets C08h through C10h.
EPM-4 Reference Manual
M
ODE
CMOS Setup / Advanced Configuration
Configuration / Operation – 13
Advertisement
Table of Contents
