Matrix Input (Mtr) - Mitsubishi MELSEC QCPU Programming Manual

Programmable logic controller
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6 BASIC INSTRUCTIONS

6.8.10 Matrix input (MTR)

Internal Devices
Set
(System, User)
Data
Bit
Word
S
D1
D2
n
[Instruction Symbol] [Execution Condition]
MTR
[Set Data]
Set Data
S
D1
D2
n
[Functions]
(1) Successively reads the input from 16 points starting from the input number designated by
multiplied by n-rows, then stores the data fetched in this operation from the device designated
by
onward.
D2
(2) One row (16 points) can be fetched in 1 scan.
(3) Fetching from the first to the nth row is progressively repeated.
(4) The first through the 16th points store the first row of data and the next 16 points store the
second row of data at the devices following the device designated by
For this reason, the space of 16xn-points from the device designated by
the MTR instruction.
(5)
is the output needed to select the row which will be fetched, and the system automatically
D1
turns it ON and OFF.
It uses the n-points from the device designated by
(6) Only device numbers divisible by 16 can be designated for
(7) The value for n2 is not between 2 to 8. (Error No. 4100)
6 - 132
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MELSECNET/10(H)
File
Direct J \
Register
Bit
Command
• Head input device
• Head output device
• Head number of device that will store matrix input data
• Number of input rows
QCPU
PLC CPU
Basic
High Performance
Usable Devices
Special
Function
Module
Word
U \G
MTR
S
D1
Meaning
.
D1
S
MELSEC-Q/QnA
QnA
Process CPU
Index
Register
Constant
Zn
n
D2
Data Type
Bit
BIN 16 bits
.
D2
are occupied by
D2
,
and
.
D1
D2
6 - 132
Q4AR
Other
,
S

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