16-Bit And 32-Bit Negation Transfers (Cml, Cmlp, Dcml, Dcmlp) - Mitsubishi MELSEC QCPU Programming Manual

Programmable logic controller
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6 BASIC INSTRUCTIONS

6.4.4 16-bit and 32-bit negation transfers (CML, CMLP, DCML, DCMLP)

Internal Devices
Set
(System, User)
Data
Bit
Word
S
D
[Instruction Symbol] [Execution Condition]
CML, DCML
CMLP, DCMLP
[Set Data]
Set Data
S
D
[Functions]
CML
(1) Inverts 16-bit data designated by
by
D
.
Before execution
After execution
DCML
(1) Inverts 32-bit data designated by
by
D
.
Before execution
After execution
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MELSECNET/10(H)
File
Direct J \
Register
Bit
Command
Command
Data to be inverted, or number of device storing this data
Number of device that will store results of inversion
S
b15
S
1
0
1
1
b15
0
1
0
0
D
S
+1
S
b15
0
S
1
1
1
+1
D
b15
0
1
0
0
D
QCPU
PLC CPU
Basic
High Performance
Usable Devices
Special
Function
Module
Word
U \G
indicates CML or DCML
P
Meaning
bit by bit, and transfers the result to the device designated
0
1
0
0
0
1
1
1
Inversion
1
0
1
1
1
0
0
0
bit by bit, and transfers the result to the device designated
b0
b15
0
0
0
0
1
1
1
Inversion
b0
b15
1
0
1
1
1
0
0
MELSEC-Q/QnA
QnA
Process CPU
Index
Constant
Register
Other
K, H
Zn
S
D
S
D
Data Type
BIN 16/32 bits
b0
0
0
1
0
b0
1
1
0
1
S
b0
0
0
0
1
1
D
b0
0
1
1
0
1
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Q4AR

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