Mitsubishi MELSEC QCPU Programming Manual page 46

2 INSTRUCTION TABLES
Category
DXOR
DXORP
DXOR
Exclusive
OR
DXORP
BKXOR
BKXORP
WXNR
WXNRP
WXNR
WXNRP
NON DXNR
exclusive
logical sum
DXNRP
DXNR
DXNRP
BKXNR
BKXNRP
REMARK
1) 1:The number of steps may vary depending on the device and type of CPU module being
used.
Component
High Performance model QCPU
Process CPU
Basic model QCPU
QnCPU
Note 1:With High Performance module QCPU, (1) requires more number of steps, while it can
process the steps faster, as compared with (2).
Note 2:The number of steps may increase due to the conditions described in Section 3.8.
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Table 2.18 Logical Operation Instructions (Continued)
Symbol
DXOR S D
(D+1, D)
DXORP S D
DXOR S1 S2 D
(S1+1, S1)
DXORP S1 S2 D
BKXORP S1 S2 D n
BKXORP S1 S2 D n
WXNR S D
(D)
WXNRP S D
WXNR S1 S2 D
(S1)
WXNRP S1 S2 D
DXNR S D
(D+1, D)
DXNRP S D
DXNR S1 S2 D
(S1+1, S1)
DXNRP S1 S2 D
BKXNR S1 S2 D n
BKXNRP S1 S2 D n
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
• Constant : No limitations
(2) When using devices other than (1)
Processing Details
(S+1, S) (D+1, D)
(S2+1, S2) (D+1, D)
(S1) (S2) (D)
(S) (D)
(S2) (D)
(S+1, S) (D+1, D)
(S2+1, S2) (D+1, D)
(S1) (S2) (D)
Nomber of basic steps
designation is K8, and which use no index modification.
3
MELSEC-Q/QnA
Execution
Condition
1
2
3
5
n
3
4
3
1
2
3
5
n
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7-16
7-18
7-20
7-22
7-26
7-22
7-26
7-28
Note 1)
5
Note 2)
3
Note 2)