Model 165 Machine Check Interrupts - IBM System/370 Manual

Figure 50.10.4 illustrates the layout and the contents of the eight-
byte machine check code stored in processor storage locations 232-239.
The machine check code indicates which type of interrupt occurred,
the validity of certain fields stored in the fixed logout area, and
the length of the stored CPU extended logout area.
Table 50.10.1 lists the machine check subclasses defined for the
Model 165. They are described in the discussion that follows.
The mask bits used to enable or disable each subclass for interrupts
are indicated and the setting of the machine check code is discussed.
PSW bit 13 and two other mask bits are used to enable and disable
machine check interrupts. The recovery mask (R) and external mask
(E) bits are contained in control register 14 and operate subject to
PSW bit 13. If PSW bit 13 is disabled, then all machine checks are
masked. If PSW bit 13 is enabled, then the settings of the two
additional mask bits determine whether or not interrupts, other than
System Damage, will be taken. Refer to Figure 50.10.4.
Table 50.10.1. Model 165 machine check interrupts
Subclass Mask Bit(s) Cause
Machine Check
System Damage PSW 13 • Unretryable CPU Hard
error
• Uncorrectable CPU
error
• Multiple-bit processor
storage error
• Storage protect key
failure
System Recovery
PSW 13
and R
• CPU error corrected Soft
by retry
• Single-bit processor
storage error
corrected by ECC
Time of Day
clock Damage
PSW 13
and
E
• Error in time of day Soft
clock
External Damage
PSW
13
and E
• Error that did not Soft
76
affect the CPU, such
as multiple-bit processor
storage error during
an I/O operation
Soft machine check interrupts on System/370 Model 165 are as follows:
• System Recovery - This interrupt occurs if both PSW bit 13 and
the recovery mask bit are on. It is caused by a successful
CPU retry or single-bit processor storage error correction.
The SR bit in the stored machine check code (bit 2) is used
to indicate the occurrence of an ECC single-bit error correction
or a successful CPU retry of a failing CPU operation (including
one caused by a buffer malfunction). The SC bit (bit 17) will
be on as well if an ECC recovery occurred.
Error recording and, possibly, buffer deletion are required
after a System Recovery interrupt.