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microprogramming required to handle the balance of the instruction
set for the Model 165 and other optional features, such as a 1000-
series compatibility feature.
WCS is also used to house diagnostic routines.
The use of some
writable control storage in the Model 165 in addition to ROS allows
nonresident diagnostics to overlay each other.
Thus more extensive
diagnostics can be provided without the necessity of adding more control
storage.
During a power-on sequence, WCS is automatically loaded with system
microcode from a removable magnetic disk cartridge contained on a
device in the console unit.
The magnetic disk cartridges sent to an
installation will be tailored to include the microcode required by
the optional features included in the system configuration.
Program States and System Interrupts
The program states in which the Model 165 is operating are reflected
in the current program status word (PSW) and in new CPU status
indicators, called control registers, located in the CPU.
Up to 16
control registers, 0-15, can be addressed; however, only 4 are
implemented in the Model 165.
They are program addressable when the
CPU is in the supervisor state.
A control register can be set with
the new LOAD CONTROL instruction, and its contents can be placed in
processor storage with the STORE CONTROL instruction.
Additional
status indicators contained in control registers are required in order
to support new system functions.
The contents, layout, and function of fixed locations 0-121 in
System/310 models are identical to these locations in Systern/360 models
with one exception.
Bit 12 in the PSW, which sets EBCDIC or ASCII
mode in System/360 models, is not used for this purpose in the Model
165.
(It must be set to zero.)
ASCII mode is not implemented in the
Model 165, nor was the mode bit supported by IBM programming systems
for Systern/360 models, since the expectation that System/360 ASCII-8
would become the ASCII standard has not been borne out.
The implementation of the machine check level of interruption in
the Model 165 has been altered considerably from its implementation
in Models 65 and 15 in order to enhance system availability (see Section
50).
However, the other four interrupt levels operate in the same
manner on the Model 165 as on Models 65 and 15.
CPU Features
Significant features of the Model 165 CPU are the following:
Expanded Instruction Set
The standard instruction set for the Systern/310 Model 165 is a
superset of that provided for System/360 Models 65 and 15.
It consists
of the System/360 instruction set plus new instructions that support
System/310 architecture and provide additional functions.
The Model
165 standard instruction set includes all general purpose and I/O
instructions and all binary, decimal, floating-point, and extended
precision floating-point arithmetic instructions.
Storage protect
and time of day clock instructions are also standard.
The new STORE
CPU ID instruction permits a program to determine the model upon which
i t is operating and provides the system serial number.
The new STORE
CHANNEL ID instruction can be used to identify the types of channels
present in the system.
Other new standard instructions are:
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