IBM System/370 Manual page 9

2
CPU retry of most failing CPU hardware operations is handled
automatically by the hardware without programming assistance.
Writable control storage (WCS) is included in addition to read-
only storage (ROS) to contain new Model 165 instructions, emulator
microcode, and CPU diagnostics.
• Relocatable emulators are provided that operate under OS control.
Concurrent execution of System/370 programs with 7000-series
programs is supported. A 7080, a 7070/7074, and a
709/7090/7094/709411 emulator are available on a mutually exclusive
basis.
• A
free-standing 3066 System Console is required. Its features are:
A buffered cathode ray tube and an alphameric keyboard for rapid
operator/system communication
An indicator viewer to display system status
A
system activity monitor to provide, via the system activity
meter, visual display of average system activity
A
microfiche document viewer for CE use
A processor storage configuration plugboard
A
device for loading WCS and diagnostic routines
• Channel features of the Model 165 are as follows:
2870 Multiplexer Channels, 2860 Selector Channels, and the new
2880 Block Multiplexer Channels can be attached - for a total of
seven addressable channels. A single 2880 channel can operate
at a 3 MB rate with attachment of an optional feature.
The Extended Channels feature permits a Model 165 to have up to
twelve addressable channels, which can support an aggregate channel
data rate in excess of nine megabytes per second.
The 2880 Block Multiplexer Channel is a superset of the 2860
Selector Channel. When used in conjunction with rotational position
sensing devices, i t can increase total system throughput by
permitting more data to enter and leave the system in a given time
period than can the 2860.
A
single 2880 channel can support
interleaved, concurrent execution of multiple high-speed I/O
operations.
Channel retry data is provided after channel errors so that error
recovery routines can retry I/O operations.
• storage features offered by the Model 165 are as follows:
A two-level memory system, consisting of fast, large-size processor
(main) storage used as backing storage for a smaller, very high-
speed buffer storage, is implemented. The CPU works mostly with
the buffer so that the effective access time for data is reduced
to a fraction of the processor storage cycle time.
8K or 16K bytes of SO-nanosecond monolithic buffer storage is
available (SK is standard). The CPU can initiate a request
for eight bytes from the buffer every 80 nanoseconds.