IBM System/370 Manual page 147

to the CPU without a processor storage reference. If the requested
data is not currently in the buffer, a processor storage fetch is made.
The data obtained is sent to the
cpu.
The data is also assigned a
buffer location and stored in the buffer. When data is stored by the
CPU, both the buffer and processor storage are updated if the processor
storage location being altered is one whose contents are currently
being maintained in the buffer.
The channels never access the buffer directly. They read into and
write from processor storage only. When a channel stores data in
processor storage, the address array is interrogated. If data from
the affected processor storage address is being maintained in the
buffer, the data is placed in the buffer as well as in processor
storage.
The entire buffer can be disabled manually by a system console
switch or via execution of a DIAGNOSE instruction. When the buffer
is disabled, all CPU fetches are made directly to processor storage
and effective system execution speed is reduced.
The 8X buffer is shown in Figure 10.15.4. It contains 64 columns
of 128 bytes each. Every buffer column is subdivided into four blocks.
A block is 32 bytes and can contain 32 consecutive bytes from processor
storage that are on a 32-byte boundary. The 8X buffer can contain
a maximum of 256 different blocks of processor storage data (4 blocks
per column times 64 columns). A valid trigger is associated with each
buffer block and is set to indicate whether or not the block contains
valid data.
Processor storage is logically divided into the same number of
columns as buffer storage: 64 or 128. While there are always four
blocks in a buffer column" the number of blocks in a processor storage
column varies with the size of processor storage. For example, when
an 8X buffer is present, bits 21-26 of the processor storage address
determine which of the 64 columns to use. As shown in Figure 10.15.4,
a processor storage column consists of 512 blocks in a system with
1024X. Any of the 512 blocks in a given processor storage column can
be placed in any of the four blocks in the corresponding buffer column.
Figures 10.15.5 and 10.15.6 show the formats used for processor and
buffer storage addressing.
The larger the processor storage size, the greater the number of
storage blocks that contend for the four blocks in the same buffer
column. If a 16K buffer is used instead of an 8K, the number of buffer
columns is doubled from 64 to 128; the number of processor storage
blocks contending for the blocks in each buffer column is thereby
halved if processor storage size remains the same. (A 1024K processor
storage divided into 128 columns has 256 blocks per column.)
The 16X buffer is provided for users with larger Model 165 processor
storage configurations that have applications such that increased
system throughput results from an increase in internal performance.
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