IBM System/370 Manual page 168

• External Damage - This interrupt occurs if both PSW bit 13 and
the external mask bit are on. The ED bit of the stored machine
check code (bit 5) will be on to indicate that the storage
control unit or processor storage is damaged but that operations
associated with the CPU were not affected because the multiple-
bit storage failure was associated with an I/O operation. When
this type of error occurs, both a soft machine check and an
I/O interrupt occur. The error is logged after the machine
check interrupt. Error recovery procedures are initiated after
the I/O interrupt.
• Time of Day Clock Damage - This interrupt occurs if both PSW
bit 13 and the external mask bit are on. The CD bit in the
stored machine check code (bit 4) will be on to indicate that
an error occurred in the time of day clock that renders the
clock invalid. Once this invalid indication has been given,
subsequent STORE CLOCK instructions cause the condition code
in the current PSW to indicate the fact that the clock is
invalid. Error logging is required as a result of clock failure.
Hard machine check interrupts on the System/370 Model 165 are as
follows:
• System Damage - This interrupt occurs if PSW bit 13 is on.
The SD bit in the stored machine check interrupt code (bit 0)
is used to indicate that an error occurred during the execution
of the instruction indicated by the machine check old PSW.
The error was either a multiple-bit processor storage failure,
a storage protection failure, a CPU error that was unretryable,
or a CPU error that could not be corrected by the CPU retry
hardware.
If a multiple-bit processor storage failure caused the interrupt,
the SE bit in the stored machine check code (bit 16) is on also,
and the address of the failing storage area is indicated in
the extended logout area. A storage protection failure is
indicated by the
KE
bit (bit 18).
A
logout to the CPU extended logout area also occurs. For a
CPU error, an extended logout occurs on the first and seventh
retry. Error logging and the execution of recovery procedures
are required after this type of interrupt.
Two modes of system operation will be used: full recording mode
and quiet, or nonrecording, mode. In full recording mode, all machine
check interrupt types cause an interrupt to be taken and logouts to
occur. This will be the normal mode of Model 165 operation. In quiet
mode, all or certain soft machine check interrupts are disabled. Quiet
mode can be used to permit system operation without error recording
for all or certain soft errors when a large number of transient
(correctable) errors are occurring. It can also be used to allow Model
165 operation under the control of an operating system without Model
165 machine check handling routines included.
A hard stop status and a hard stop bit have been defined for the
Model 165. The hard stop bit is located in control register 14 with
the other mask bits discussed. If a hard stop condition occurs, the
Model 165 system ceases all operations immediately without the
occurrence of a logout to the fixed area. Hard stop is initiated by
hardware rather than by programming.
When enabled, a hard stop occurs if a System Damage hard machine
check type of error is detected when all machine check interrupts are
disabled or during the processing of a previous machine check error.
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