Recovery Management Support - IBM System/370 Manual

Implementation of a hard stop prevents system operations from continuing
when the nature of the machine malfunction prevents the system from
presenting meaningful status data.
The state of the Model 165 after IPL or a system reset is:
1. CPU retry and an extended logout are disabled when a CPU error
occurs. A hard machine check interrupt results on any CPU
error, including those caused by a buffer malfunction.
2. Recovery reports are disabled. Therefore, single-bit processor
storage error corrections do not cause a soft machine check
interrupt.
3. External damage reports are enabled. A double- or multiple-
bit processor storage failure associated with an I/O operation
and damage to the time of day clock cause a machine check
interrupt.
4. PSW bit 13 is normally enabled by the IPL PSW (it is disabled
by system reset) so that System Damage machine checks
(unretryable CPU failures, unsuccessfully retried CPU errors,
storage protection failures, and multiple-bit processor storage
errors associated with the CPU) cause a hard machine check
interrupt.
5. Hard stop is enabled.
6. CPU extended logout is enabled and control register 15 points
to location 512 as the beginning of the CPU extended logout
area.
1. Channel logouts are disabled.
A machine check situation in a Model 65 or 15 results from hardware
detection of a machine malfunction or of a parity error. Bad parity
can occur in main storage, in local storage, in a register, in an
adder, etc. Error correction hardware is not included in these two
models. If the machine check mask in the current PSW (bit 13) is
enabled, a machine check on Models 65 and 15 causes an interrupt and
a diagnostic scan-out occurs, starting at location 128.
If recovery management support (RMS) is included in an OS control
program for the Model 65" the MCH routine gains CPU control to record
the error and to attempt corrective procedures after the machine check
interrupt. Model 65 MCH performs programmed instruction retry for
certain instructions only. Alternately, if an SER routine is present,
the error is only logged, since a retry of the failing operation is
not provided by this routine.
RECOVERY MANAGEMENT SUPPORT (RMS), - OS MFl' AND MVT
MCH and CCH Routines
RMS for the Model 165 consists of extensions to the facilities
offered by RMS routines currently provided for Models 65 and up. The
two RMS routines, machine check handler (MCH) to handle machine check
interrupts and channel check handler (eCH) to handle certain channel
errors, will be included automatically in MFT and MVT control programs
generated for the Model 165.
The two primary objectives of RMS are (1) to reduce the number of
system terminations that result from machine malfunctions and (2) to
minimize the impact of such incidents. These objectives are
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