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13220
Processor Module
13220-91087/08
Rev
JAN-04-82
3.1.3
I/O Ports
CMUS
The Z80A
is
capable of
addressing 2S6 different
input/output ports.
I/O addresses
froM the
ZaOA
appear on
address bits
AO-A7
and
the
accuMulator contents appear on bits A8-A1S.
I/O
addresses
0-7FH are
used
to
access
locations
in the nonvolatile CMOS
RAM,
U73,
where
configuration data is stored.
Since the CMOS RAM is not fast enough to
respond
within the I/O cycle tiMe a wait state is generated
(by U6l0)
each tiMe the CMOS RAM is accessed.
Diodes CR6-CR8 ensure that around
S volts
is always on
t~e
CMOS supply pin.
EMMitter follower Circuit,
Q3,
Makes sure
that during
a
power off the CMOS
is
always
disabled
before the l80A
buses
beCOMe
undefined
and reMains
so
until buses
beCOMe
defined
at power on.
During
power off the battery Maintains
CMOS contents.
If power on configuration is to be fixed,
the COMS RAM
May be replaced by an HM7611 PROM (however it Must be realized that the
standard read/COMpleMent/write test for the CMOS self test would show a
CMOS error since the prOM cannot be written).
DATACOMM
The
SY6SS1
Asynchronous COMMunications Interface Adapter perforMS the
parallel to serial conversion, error detection and baud rate generation
functions required for serial data COMMunication.
It
appears to
the
laOA
as four read only and four write only ports
with
address bit TA2
selecting the read/write function.
This is done to COMpensate for the
unique tiMing
of
the 6500 series devices.
The SY6551 is selected by
the
rising
edge
of SELDC
which
is
inverted
frOM U24,
the 1 of 8
decoder.
The addresses of the SY6SS1 (U613) are AO-A7H.
The
status
inputs
of
the SY6SSl
produce
undesirable
results
and
therefore are
forced to their
active low
states while
the necessary
status signals are routed
through another
port.
RS-232 line driver,
USi4, and receiver, U614, are
~sed
to convert frOM TTL levels to RS-232
levels
(+-12V)
and vice versa.
TranSMitted signals are:
send data
(SD),
terMinal ready
(TR),
request to send (RS) and optional control
driver 1 (OCD1).
Received signals are:
receive
d~ta
(RD),
data Mode
(DM), optional control receiver 1 (OCR1), and
clea~
to send (eS).
The datacoMM subsysteM operates in an asynChronous, full-duplex, point-
to-point
environMent.
Characters
May
be
tranSMitted
and received
siMultaneously
(full-duplex) with character flow occurring over randOM
tiMe
intervals
(asynchronous).
To achieve hardware
synchronization
each character is fraMed by a start bit and a stop bit
(2
stop bits at
110 baud).
The addition of the fraMing bits for tranSMitted characters
and the detection
of fraMing bits for the received characters are done
by the SY65S1.
The parity
(for error detection)
of the character is
selectable
(in the datacoMM configuration Menu)
and is also generated
and detected by the SY6SS1 which reports errors
(parity,
fraMing, and
overrun)
to the ZaOA by Means of a status register in the SY6SS1 which
is
read
when a character
is
received.
The
data tranSMission
and
reception rates are set by the ZaOA in an internal reqister
within the
SY6SS1.
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