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3.3.2
VERTICAL. TIMING
The 26
active video
rows
of
the
display each require 1S horizontal
scans for a total of
390
active video scans.
After the last scan line
of the
last row is displayed,
a
vertical
blank signal
is activated
which disables the electron beaM during the vertical retrace tiMBo
The
beaM is enabled
again on
the first scan
line of the first row.
The
duration of the vertical blank interval depends upon
the
occurance of
the vertical
sync
signal which triggers the
vertical retrace.
This
vertical sync
tiMing depends in turn
on the frequency
with which the
fraMe
(one
entire display)
is refreshed.
This fraMe
rate
May
be
configured
to
either
SO
or
60
Hz
corresponding
to the
AC
line
frequencies
in foreign
countries or
the
U.S.
to eliMinate display
interference between
the power supply
and CRT.
The
following table
describes
the
tiMing
relationships between
the
vertical
blank and
vertical sync signals and the fraMe rate.
TABLE b.O
FraMe TiMing
FraM(~
Rat(~
60
Hz
I
SO
Hz
Delay after v. blank to
v. sync
(=1=
scan lines)
0
v. sync width
(I
scan lines)
19
64
v. blank duration (I scan lines)
25
1.08
Total
i
scan lines per fraMe
415
Display MeMory addressing
Section
3.2.2 describes how the
eRTC
perforMS DMA
to load
the line
buffers with character and
enhanceMent data
for display.
Before
it
perforMS DMA,
the CRTC Must be loaded with a starting address
(called
the
row-start address).
Each tiMe the
CRTC is enabled it fetches 80
consecutive bytes
of data starting
frOM the
row
start
address
and
places it into one of the recirculating line buffers.
The
Z80A
Maintains
a
table
of 24
row
start addresses
in
MeMory
indicating the addresses of the
first byte of
character data for each
of the character rows being displayed.
Rows 2S and 26 contain the soft
key labels and are always accessed frOM fixed locations.
This table is
actually a subset
~f
a larger table
which contains row-start addresses
for all 48 display rows.
The address of the first enhanceMent byte of
a row is the first character byte address offset by 80.
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