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13220
Processor Module
13220-91087/17
Rev
JAN-04-82
3.3.3
Two
scan lines
prior
to the NBUSREQ
signal
being activated
a non-
Maskable interrupt
(NMI)
is generated which causes the Z80A to branch
to the NMI
service
routine
after COMpleting the current instruction.
Part of this service routine writes
the row-start address for the next
DMA into the rowstart
register of the CRTC.
The row-start address is
written into the CRTC via the address bus itself.
At
the saMe
tiMe,
bits TA13 and TA12 are written into the 74LS17S U7S, which provides the
upper
bits of the RAM address for DMA.
The ZaOA reads the
row start
address froM the table,
adds the 80 byte
offset for
enhanceMent data
DMA, Masks bits TA1S and TA14 to a 1 and 0 respectively and then writes
a
02H
to
this address.
By
Masking
bits TA1S and TA14 the address
corresponds to a ROM location, which of course can't be written.
These
bits are decoded by part of U27 and U32,
along with TNMREQ and
TNWR
to
generate
the
register load signal
(U412 pin
38)
which
latches the
address into the
eRTC
and U7S for use during the next DMA cycle.
The
data bits
ZDO and
ZD1 select
the register to be written to,
in this
case,
the row-start register.
The NMI service routine keeps count of
the
next
row
to be
displayed
in order to deterMine which row start
address
to send to the CRTC next.
Since
NMI can be
disabled for an
indefinate period
(for exaMple during a RAM test) it is resynchronized
every
fraMe by reading the
VBLANK signal
through the
systeM
status
port.
Character display
At any
given tiMe the
characters for the current row being
displayed
are held
in the recirculating
line buffer U39.
The
character codes
output
frOM this line buffer are resynchronized to the character clock
through
the octal
latch,
U310,
frOM which
they
are
sent
to
the
character ROM,
U311.
This ROM contains the dot pattern for each scan
line of each each possible character code.
The standard character set
uses the ASCII character code to represent
the 128 possible characters
in
the
set.
The
first 32
characters of
the
set are
the control
characters
(escape,
line feed,
carriage return,
etc.)
while those
reMaining
are the alphanUMeric and punctuation characters.
These 128
characters are represented in bits XO-X& with X7 being a O.
These bits
along with the scan line count
beCOMe addresses
for the dot data frOM
the character ROM.
Therefore,
11 address bits are required,
Meaning
that a 2K byte ROM May be used to contain the dot data for the standard
character set.
Bit X7 will then serve as an active low chip select.
By usinq a
4K
byte character ROM,
two COMplete character sets May be
displayed.
In this case bit X7 selects between the two character sets.
Likewise
an
BK
byte
ROM
can
store four COMplete,
128
character,
character sets.
The scheMatic shows a signal frOM the enhanceMent data
latch, U29 pin lS,
which is inverted by U212, and sent to U311 pin 21.
This
signal
is used
to address
the
8K
byte
character ROM
on
4K
boundaries.
This COMbined with bit
X7
frOM the character data latch
allows
selection
of any of the
four character sets.
This upperMost
address bit beCOMes a chip select for 2K or 4K character ROMs.
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