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13220
Processor Module
13220-91087/09
Rev
JAN-04-82
Rates are selectable
(in the datacoMM configuration Menu)
frOM 110 to
9600 baud.
The
datacoMM status inputs and outputs
provide the
necessary control
lines to connect the terMinal to a host COMputer
via
a
ModeM,
or
to
provide direct hardware handshaking between the terMinal and host.
At
power-on
the
TR
and
RS
lines
are activated to
indicate
that the
terMinal is ready.
Upon receipt of a ModeM disconnect escape sequence
(esc f)
the
TR
line is brought
inactive for .about
two seconds
to
disconnect the ModeM.
The presence of a ModeM connection
is detected
by
DM
which
causes the indicator
"LED"
(an
asterisk
'*')
to
be
displayed on the bOttoM center of the display.
The CS signal frOM the
host when active allows the terMinal to tranSMit data and goes inactive
to halt tranSMission
(the terMinal May ignore CS depending on datacoMM
configuration).
The state
of OCDl
is controlled
by a configuration
strap with its default state being low
(inactive).
This line selects
the
ModeM
rate for dual speed ModeMS.
OCRl is Monitored in datacoMM
self test to detect the presence of the loopback test hood.
All ModeM
status lines are active high (+12V).
Upon
receipt
of
a
character frOM datacoMM
the SY6SS1 generates
an
interrupt signal (NINT) to the lBOA.
This causes the ZaOA to branch to
the datacoMM interrupt
service routine which reads the SY6S51
status,
clearing
the
interrupt,
and
if
no errors are present,
inputs
th~
character and places it into the datacoMM
buffer
in RAM.
Characters
for
which errors
(parity,
fraMing or
overrun)
are
present cause a
delete character to be placed in the buffer.
Teus PORTS
The reMaining I/O ports
are
buffered
to the
ZaOA
data
bus by
the
biderectional
bus driver,
U37.
This
was done
because of
data bus
loading.
The signal TNRD selects the direction of the driver which is
enabled for all I/O accesses except CMOS RAM and datacOMM.
U25 forMS
the keystatus port
located at address
80H.
The keystatus
port returns the status of 8 keys at a tiMe,
which keys are deterMined
by
th~
keyboard/display
port
(U26).
Four
bits
of the key
address
(colUMn address) are supplied by U26 (located at address B8H) and three
More frOM the eRTC scan line outputs (row address).
As the row address
(scan line count) frOM the CRTC change,
keystates are clocked into the
keystatus shift register (a high bit indicating key active)
frOM which
they are later read.
The colUMn address is increMented (during an NMI)
for
each of the first sixteen display rows thereby scanning the entire
range of keyboard addresses.
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