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04···82
During an instruction (opcode)
fetch the Z80A activates the NM1 signal
to indicate that an instruction fetch cycle is in process.
This signal
is used to provide an early enable of the ROM being addressed during an
opcode fetch therby allowing the use of ROMs with an access tiMe on 350
ns froM address or 300 ns froM enable (note that an opcode fetch is
o~e
clock cycle shorter than a MeMory read operation)
without wait states.
During
a MeMory read frOM ROM the
TNMREQ and
TNRD signals
go active
G~nabling
th(~
addl'f.~Ssf:~d
ROM.
Data is
r'f.~quired
valid
app('OXiMatf.~ly
470
n
~:)
fro M
i:l
d d
l' (0 S
s) the r e
of
0
r' e n () wa i t s
t
,1
t e s a r
(-?
r
(~q
u ire d for M (-?
til 0
r y rea d s
even
when
using 450 ns EPRUMs.
Note that data is placed directly on
thE' Z80t-1 dati-'l but:; without buP·fering.
RandoM-acceSS-MeMory
The RAM subsysteM has been designed around the MK4ll6-2 (or equivalent)
16K x 1 bit dynaMic RAMs.
The MK4116-2
has a MiniMUM
access tiMe of
150 ns and MiniMUM cycle tiMe of 320 ns.
U41-44 and US1-S4 supply data
bits TDO-TD7 respectively to provide the 16K bytes of RAM data storage.
Th(~
I~AM~;;
ar'e
acce~)~;(~d
in thl'(;:O(-?
ways:
by
the ZaOA for
M~?MOr'y
read or
Wf':i.
te
clC:ce5se~)
by
the
lBOA
d U1' ing
a
l'efl'€-~sh
c yc Ie and by the
CI~TC
during
a DMA
(direct-MeMory-access)
cycle.
Each
of
the three
is
discussed below.
Refer to figure 6.0 for RAM tiMing.
ZUOA
I~EAD/WI~
ITE
A Z80A access to RAM is
initiated by lowering
the TNMREQ signal at an
address location between COOOH and FFFFH (RAM address range).
Prior to
TNMREQ going
low the output
of U77 would
be high
causing l's to
be
shifted through the shift register)
U510, by DRCX.
As TNMREQ goes low
(TNRFSH is high) the output of U77 goes low also.
As the clock occurs,
O's are shifted through the shift register causing
outputs QA-QD to go
low in turn.
This produces the RAM tiMing sequence as follows:
NRAS-
strobes
in
row
address)
MUX-changes RAM address
inputs
to
colUMn
address)
NCAS-strobes
in colUMn address
and
activates internal
RAM
circuitry to access the addressed cell.
Data ouput on MDO-MD7 is vaild
100 ns frOM NCAS.
When
the
Z80A
is
finish~d
accessing the RAM the
TNMREQ signal goes high and 1'5 are shifted
through the shift register
COMpleting the RAM cycle.
If the
Z80A is
perforMing
d
read operation the TNRD line
is
lowered
along with TNMREQ
(TNWR reMains high).
The TNRD signal is gated with
the output of U77 to enable the transparent latch, U62) during the read
operation.
When
the
NMUX
signal goes high
(as MUX
goes low)
the
transparent latch beCOMes transparent) that is,
the outputs follow the
inputs)
placing
the RAM outputs
on
the ZBOA data
bus.
The
latch
outputs are enabled until TNRD and TNMREQ go high again.
For a
write
operation,
the
ZaOA lowers TNMREQ and places the output
data on the data bus.
ApproxiMately one Z80A clock later the TNWR line
goes low
strobing the data
into the internal
data latch in
the RAM.
The TNRD signal will be high
disabling
the transparent latch so RAM
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