Sysreset; Osc; Ccc; Setting Up The Demo Design - Microsemi IGLOO2 FPGA DSP FIR Filter Demo Manual
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Also See for IGLOO2 FPGA DSP FIR Filter:
- Application note (102 pages) ,
- User manual (64 pages) ,
- Manual (15 pages)
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IGLOO2 FPGA DSP FIR Filter
2.3.2.7 SYSRESET
The SYSRESET IP provides the power on reset signal.
2.3.2.8 OSC
The OSC IP is configured as an RC oscillator to provide the 50 MHz signal to the clock conditioning
circuit
(CCC).
2.3.2.9 CCC
The CCC IP is configured to provide a 150 MHz clock
and resource usage
2.4
Setting Up the Demo Design
The following steps describe how to setup the hardware demo:
1.
Connect the jumpers on the IGLOO2 Evaluation Kit board, as shown in
Table 3 • IGLOO2 FPGA Evaluation Kit Jumper Settings
Jumper
J22
J23
J24
J8
J3
CAUTION: While making the jumper connections, the power supply switch SW7 must be switched
OFF.
2.
Connect the Power supply to the J6 connector, switch ON the power supply switch, SW7.
3.
Connect the FlashPro4 programmer to the J5 connector of the IGLOO2 Evaluation Kit board.
4.
Connect the host PC USB port to the J18 USB connector on the IGLOO2 Evaluation Kit board using
the USB Mini-B cable.
summary,
refer to
"Appendix: SmartDesign Implementation" on page
Pin (From)
1
1
1
1
1
Revision 6
signal.
For detailed smart design implementation
Pin (To)
2
2
2
2
2
30.
Table
3.
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