Sign In
Upload
Manuals
Brands
Microsemi Manuals
Microcontrollers
M2S025
Microsemi M2S025 Manuals
Manuals and User Guides for Microsemi M2S025. We have
1
Microsemi M2S025 manual available for free PDF download: User Manual
Microsemi M2S025 User Manual (124 pages)
SoC FPGA and IGLOO2 FPGA Fabric
Brand:
Microsemi
| Category:
Microcontrollers
| Size: 2 MB
Table of Contents
Table of Contents
3
1 Revision History
10
Revision 7.0
10
Revision 6.0
10
Revision 5.0
10
Revision 4.0
10
Revision 3.0
10
Revision 2.0
11
Revision 1.0
11
Revision 0.0
11
2 Fabric Architecture
12
Introduction
12
Fabric Resources
13
Figure 1 Smartfusion2/Igloo2 Fabric Architecture for M2S050/M2GL050
13
Table 1 Fabric Resources for Smartfusion2 Devices
13
Architecture Overview
14
Logic Element
14
Figure 2 Functional Block Diagram of Logic Element
14
Table 2 Fabric Resources for IGLOO2 Devices
14
Interface Logic Element
15
I/O Module
15
FPGA Routing Architecture
16
Figure 3 Functional Block Diagram of MSIO
16
Figure 4 Logic Cluster Top-Level Layout
17
Figure 5 Interface Cluster
17
Figure 6 Fabric Routing Structure
18
Fabric Array Coordinate System
19
Figure 7 M2S050/M2GL050 and M2S060/M2GL060 Fabric Logical Coordinates
19
Figure 8 M2S025/M2GL025 Fabric Logical Coordinates
20
Figure 9 M2S010/M2GL010 Fabric Logical Coordinates
20
Table 3 Fabric Array Coordinate Systems
21
3 Lsram
22
Introduction
22
Features
22
LSRAM Resources
22
Table 4 Smartfusion2 and IGLOO2 LSRAM (18Kb Blocks) Resource Table
22
Functional Description
23
Figure 10 Simplified Functional Block Diagram for LSRAM
23
Port List
24
Table 5 Port List for LSRAM Macro (RAM1KX18)
24
Port Descriptions
25
Table 6 Depth/Width Mode Selection
25
Table 7 Read/Write Operation Selection
25
Table 8 Address Bus Used and Unused Bits
26
Table 9 Data Input Buses Used and Unused Bits
26
Table 10 Data Output Buses Used and Unused Bits
27
Table 11 Port Select Control Signals
27
Memory Modes
29
Dual-Port Mode
29
Figure 11 Data Path for Dual-Port Mode
29
Two-Port Mode
30
Figure 12 Data Path for Two-Port Mode
30
Table 12 Data Width Configurations for LSRAM in Dual-Port Mode
30
Table 13 Data Width Configurations for LSRAM in Two-Port Mode
31
Operating Modes
32
Read Operation
32
Figure 13 Read Operation Timing Waveforms
33
Write Operation
34
Figure 14 RADDR Synchronizer
34
Table 14 Read Operation Timing Parameters
34
Figure 15 Write Operation Timing Waveforms
35
Table 15 Write Operation Timing Parameters
35
Reset Operation
36
Block Select Operation
36
Figure 16 Asynchronous Reset Operation
36
Table 16 Asynchronous Reset Timing Parameters
36
Figure 17 Block Select Timings
37
Table 17 Block Selection Timing Parameters
37
Collision
38
How to Use LSRAM
38
Design Flow
38
Table 18 Collision Operation Description
38
Figure 18 Ports of the LSRAM Configured as Dual-Port SRAM - DPSRAM Macro in Libero Soc
39
Table 19 Port Description for the DPSRAM Macro
39
Figure 19 Ports of the LSRAM Configured as Two-Port SRAM - TPSRAM Macro in Libero Soc
40
Table 20 Port Description for the TPSRAM Macro
40
Figure 20 Ram1Kx18 Macro
41
Figure 21 Coreahblsram IP in Libero Soc
41
Figure 22 Coreapblsram IP in Libero Soc
42
Table 21 Port Description for the Coreapblsram IP
42
Table 22 Port Description for the Coreahblsram IP
42
LSRAM Use Model
43
Figure 23 Two-Port SRAM with W36 and R18
44
Table 23 Two-Port Configurations Requiring Two LSRAM Blocks
45
4 Micro SRAM (Μsram)
46
Introduction
46
Features
46
Μsram Resource Table
46
Table 24 Smartfusion2 and IGLOO2 Μsram (1Kb Blocks) Resource Table
46
Functional Description
47
Architecture Overview
47
Figure 24 Simplified Functional Block Diagram of Μsram
47
Port List
48
Table 25 Port List for Μsram
48
Port Description
49
Table 26 Width/Depth Mode Selection
49
Table 27 Address Bus Used and Unused Bits
49
Table 28 Data Input Buses Used and Unused Bits
50
Table 29 Data Output Buses Used and Unused Bits
50
Table 30 Port Select Control Signals
51
Operating Modes
53
Read Operation
53
Figure 25 Timing Waveforms for Synchronous-Asynchronous Read Operation
54
Table 31 Timing Parameters for Synchronous-Asynchronous Read Operation
54
Figure 26 Timing Waveforms for Synchronous-Synchronous Read Operation
55
Table 32 Timing Parameters for Synchronous-Synchronous Read Operation
55
Figure 27 Timing Waveforms for Synchronous Latched Read Operation
56
Table 33 Timing Parameters for Synchronous Latched Read Operation
56
Figure 28 Timing Waveforms for Read Operations with Asynchronous Inputs Without Pipeline Registers
57
Figure 29 Timing Waveforms for Read Operations with Asynchronous Inputs with Pipeline Registers
57
Table 34 Timing Parameters of the Asynchronous Read Mode Without Pipeline Registers
57
Table 35 Timing Parameters of the Asynchronous Read Mode with Pipeline Registers
57
Write Operation
58
Figure 30 Timing Waveforms for Read Operations with Asynchronous Inputs with Latched Outputs
58
Table 36 Timing Parameters of the Asynchronous Read Mode with Latched Outputs
58
Reset Operation
59
Figure 31 Timing Waveforms for the Write Operation
59
Table 37 Timing Parameters of the Write Operation
59
Figure 32 Timing Waveforms for Asynchronous Reset
60
Figure 33 Timing Waveforms for Synchronous Reset
60
Table 38 Timing Parameters of the Asynchronous Reset
60
Collision
61
Table 39 Timing Parameters of the Synchronous Reset
61
Table 40 Collision Scenarios
61
How to Use Μsram
62
Design Flow
62
Figure 34 Μsram IP Macro in Libero Soc
62
Table 41 Port Description for the Μsram-IP Macro
62
Figure 35 Ram64X18 Macro
64
5 Math Blocks
65
Introduction
65
Features
65
Math Block Resource Table
65
Table 42 Smartfusion2 and IGLOO2 Math Blocks Resource
65
Functional Description
66
Architecture Overview
66
Figure 36 Functional Block Diagram of the Math Block
66
Figure 37 Functional Block Diagram of the Math Block in Normal Mode
67
Figure 38 Functional Block Diagram of the Math Block in DOTP Mode
67
Table 43 Truth Table for Propagating Operand D of the Adder or Accumulator
68
How to Use Math Blocks
69
Design Flow
69
Figure 39 Math Block Macro
70
Table 44 Math Block Pin Descriptions
71
Math Block Use Models
76
Figure 40 Non-Pipelined 35 X 35 Multiplier
77
Figure 41 Pipeline 35 X 35 Multiplier
77
Figure 42 9-Bit Complex Multiplication Using DOTP Mode
78
Figure 43 Rounding Using C-Input and CARRYIN
79
Table 45 Rounding Examples
79
Figure 44 Rounding and Trimming of the Final Sum
80
Figure 45 Rounding and Trimming of the Final Sum
80
Coding Style Examples
81
6 I/Os
86
Introduction
86
Functional Description
86
Figure 46 I/O Interconnection
87
Receive Buffer
88
Transmit Buffer
88
Figure 47 IOA Architecture
89
Figure 48 DDR Support in Low Power Flash Devices
89
Low-Power Exit
89
On-Die Termination
90
I/O Banks
90
Simultaneous Switching Noise
90
GND Bounce and VDDI Bounce
90
Figure 49 a Sample Switching Output Buffer Showing Parasitic Inductance
91
Figure 50 Basic Block Diagram of Quiet I/O Surrounded by SSO Bus
91
Table 46 MSIO SSO Guidelines for M2S010 - FG484 Device
92
Table 47 MSIOD SSO Guidelines for M2S010 - FG484 Device
92
Table 48 DDRIO SSO Guidelines for M2S010 - FG484 Device
92
Table 49 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S025 - FG484 Device
93
Table 50 MSIO SSO Guidelines for M2S050 - FG896 Device
93
Table 51 MSIOD SSO Guidelines for M2S050 - FG896 Device
93
Table 52 DDRIO SSO Guidelines for M2S050 - FG896 Device
94
Table 53 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S060 - FG676 Device
94
Table 54 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S090 - FG676 Device
94
Table 55 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S090 - FCS325 Device
95
Table 56 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S150 - FC1152 Device
95
Supported I/O Standards
96
Table 57 Supported I/O Standards
96
Single-Ended Standards
97
Voltage-Referenced Standards
97
Differential Standards
98
Table 58 IOA Pair Design Rules
98
Table 59 Status of the
98
I/O Programmable Features
99
Programmable Slew-Rate Control
100
Figure 51 Programmable Slew-Rate
100
Table 60 Smartfusion2 and IGLOO2 I/O Features
100
Table 61 Programmable Slew Rate Control
100
Programmable Input Delay
101
Programmable Weak Pull-Up and Pull-Down
101
Figure 52 Programmable Input Delay
101
Table 62 Table
101
Programmable Schmitt Trigger Receiver
102
Programmable Pre-Emphasis
102
Figure 53 Programmable Weak Pull-Up and Pull-Down
102
Figure 54 Programmable Schmitt Trigger Receiver
102
Bus Keeper
103
Figure 55 Programmable Pre-Emphasis
103
Figure 56 Bus Keeper Configuration in I/O Editor
103
Table 63 I/O Programmable Features and Standards
103
Receiver ODT Configuration
104
Receiver ODT Configuration for MSIO and MSIOD Banks
105
Figure 57 Receiver ODT Configuration
105
Receiver ODT Configuration for DDRIO Banks
106
Table 64 ODT Impedance Values
106
Table 65 ODT Configuration Options for MSIO, MSIOD, and Ddrios
107
Table 66 DDRIO ODT Configuration- for I/O Connected to Fabric
108
Table 67 DDRIO ODT Configuration- for I/O Connected to DDR Controller
108
Driver Impedance Configuration
109
Figure 58 Output Drive Impedance
109
Table 68 Driver Impedance Configurations
109
Driver Impedance Configuration for Ddrios
110
Driver Impedance Configuration for Msio/Msiods
110
Table 69 Driver Impedance Configurations for Msio/Msiods
110
Table 70 Driver Impedance Configurations for Ddrios
110
I/O Buffer Structure
111
Internal Clamp Diode
111
Figure 59 Driver Impedance Configurations for Msio/Msiods
111
Table 71 Driver Impedance Configurations for Ddrios Without DDR Controller
111
Low-Power Signature Mode and Activity Mode
112
Signature Mode
113
Activity Mode
113
3.3 V Input Tolerance in 2.5 V MSIOD/DDRIO Banks
113
Figure 60 Simulation Setup
113
Input Tolerance and Output Driving Compatibility (Only MSIO)
114
5 V Input Tolerance
114
Table 72 Table 73 F
114
Figure 61 5 V-Input Tolerance Solution 1
115
Figure 62 5 V Input Tolerance Solution 2
115
Output Driving Compatibility
116
I/Os in Conjunction with Fabric, MDDR/FDDR, and MSS/HPMS Peripherals
116
Ddrios with MDDR/FDDR
116
Ddrios with Fabric
116
Figure 63 5 V Input Tolerance Solution 3
116
Table 74 Slew Rate Control
116
Msios/Msiods with MSS or HPMS Peripherals
117
Msios/Msiods with Fabric
117
Jtag I/O
117
Table 75 JTAG Pin Description
117
Table 76 Recommended Tie-Off Values for the TCK and TRST Pins
118
Dedicated I/O
119
Device Reset I/O
119
Crystal Oscillator I/O
119
Figure 64 Chip Level Resets from Device Reset
119
Table 77 Device Reset I/O Pin
119
Table 78 Crystal Oscillator I/O Pins
119
Serdes I/O
120
7 Glossary
121
Acronyms
121
Terminology
123
Advertisement
Advertisement
Related Products
Microsemi M2S005
Microsemi M2S010
Microsemi M2S050
Microsemi M2S060
Microsemi M2S090
Microsemi M2S150
Microsemi M2GL005
Microsemi M2GL010
Microsemi M2GL150
Microsemi M2GL025
Microsemi Categories
Motherboard
Microcontrollers
Power Tool
Switch
Network Hardware
More Microsemi Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL