Seco Qseven Q7-974 User Manual page 28

Rel. 2.0 comliant module with the intel bay trail family system-on-chips

Hide thumbs

Table Of Contents

Table of Contents

3.2.3.1

PCI Express interface signals

Q7-974 can offer externally three PCI Express lane, which are directly managed by Intel

PCI express Gen 2.0 (5Gbps) is supported.

Here following the signals involved in PCI express management

PCIE0_TX+/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair

PCIE0_RX+/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair

PCIE1_TX+/PCIE1_TX-: PCI Express lane #1, Transmitting Output Differential pair

PCIE1_RX+/PCIE1_RX-: PCI Express lane #1, Receiving Input Differential pair

PCIE2_TX+/PCIE2_TX-: PCI Express lane #2, Transmitting Output Differential pair

PCIE2_RX+/PCIE2_RX-: PCI Express lane #2, Receiving Input Differential pair

PCIE_CLK_REF+/ PCIE_CLK_REF-: PCI Express Reference Clock, Differential Pair. Please consider that only one reference clock is supplied, while there are three

different PCI express lanes. When more than one PCI Express lane is used on the carrier board, then a zero-delay buffer must be used to replicate the reference

clock to all the devices.

PCIE_WAKE#: Qseven

Module's Wake Input, it must be externally driven by devices requiring waking up the system. Since it is an Active-Low Input to the

module, this signal is pulled-up with a 27kΩ resistor to +3.3V_A power rail. On the carrier board, connect it directly to the PCI-e/miniPCI-e connector's WAKE#

signal, or to WAKE# signal of any eventual PCI-e Controller present on the Carrier Board.

PCIE_RST#: Reset Signal that is sent from Qseven

to drive externally a single RESET Signal. In case Reset signal is needed for multiple devices, it is necessary to provide for a buffer on the carrier board.

Q7-974

Module to any PCI-e device available on the carrier board. It is a 3.3V active-low signal; it can be used directly

Atom E38xx SOCs (all versions).

Table of Contents