Terasic TR5-F40W User Manual
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Terasic TR5-F40W User Manual

Altera stratix v
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TR5-F40W
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June 20, 2018

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Summary of Contents for Terasic TR5-F40W

  • Page 1 TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 2: Table Of Contents

    ......................52 LASH ROGRAMMING WITH SERS ESIGN 4.4 R ..........................54 ESTORE ACTORY ETTINGS PROGRAMMABLE OSCILLATOR CHAPTER 5 ....................56 5.1 O ................................56 VERVIEW 5.2 S 570 E (RTL) ............................60 XAMPLE TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 3: Tr5-F40W User

    5.3 S CDCM P II) ......................68 ROGRAMMING ADDITIONAL INFORMATION ............................. 73 TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 4: Chapter 1 Overview

    The Stratix® V GX FPGA features 340K logic elements and integrated transceivers that transfer at a maximum of 12.5 Gbps, allowing the TR5-F40W to be fully compliant with version 3.0 of SATA, version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 10G SFP+ modules.

  • Page 5: Port

    One HSMC Connector  System Monitor and Control o Temperature sensor o Fan control  Power o PCI Express 6-pin power connector, 12V DC Input o PCI Express edge connector power  Mechanical Specification TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 6: Block Diagram

    PCI Express standard-height and half-length Figure 1-1 shows the block diagram of the TR5-F40W board. To provide maximum flexibility for the users, all key components are connected with the Stratix V GX FPGA device. Thus, users can configure the FPGA to implement any system design.
  • Page 7  1 SMA connector for external clock input HSMC Connector  Total of 8 pairs transceivers at data rate up to 12.5Gbps  Total of 18 LVDS channels (also can be configured as single-end signals)  Input and output clock TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 8  Support for PCIe Gen1/2/3  Edge connector for PC motherboard with x8 or x16 PCI Express slot Power Source  PCI Express 6-pin DC 12V power  PCI Express edge connector power TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 9: Chapter 2 Board Components

    This chapter introduces all the important components on the TR5-F40W. Figure 2-1 is the top and bottom view of the TR5-F40W development board. It depicts the layout of the board and indicates the location of the connectors and key components. Users can refer to this figure for relative location of the connectors and key components.

  • Page 10: Configuration , Status And Setup

     Connect your PC to the FPGA board using a mini-USB cable and make sure the USB-Blaster II driver is installed on your PC.  Launch Quartus II programmer and make sure the USB-Blaster II is detected.  In Quartus II Programmer, add the configuration bit stream file (.sof), check the associated TR5-F40W User www.terasic.com Manual...
  • Page 11 I/O standard by choosing the associated positions on the header. Please refer to Table 2-2 for more details. Note: removing or mounting all of the jumpers will force an output of 1.5V, and will incur the risk of damaging your FPGA. TR5-F40W User www.terasic.com Manual...
  • Page 12 Off : Disable x1 presence detect On : Enable x4 presence detect SW8.2 PCIE_PRSNT2n_x4 Off : Disable x4 presence detect On : Enable x8 presence detect SW8.3 PCIE_PRSNT2n_x8 Off : Disable x8 presence detect TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 13 Setting SW5 to the top specifies the default factory image to be loaded, as shown in Figure 2-5. Setting SW5 to low specifies the TR5-F40W to load a user-defined image, as shown in Figure 2-6. Figure 2-5 DIP switch for Image Select – Factory Image Load...
  • Page 14 On : Disable On-Board USB Blaster SW6.1 On-Board USB Blaster Off : Enable On-Board USB Blaster SW6.2 On : Disable HSMC JTAG chain SW6.3 HSMC JTAG Off : Enable HSMC JTAG chain SW6.4 TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 15: General User Input /Output

    High Logic Level when the button is not pressed BUTTON2 2.5-V PIN_B17 BUTTON3 2.5-V PIN_A17  User-Defined Slide Switch There are four slide switches on the FPGA board to provide additional FPGA input control. When a TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 16 LEDs from the designs loaded into the Stratix V GX device. Each LED is driven directly by the Stratix V GX FPGA. The LED is turned on or off when the associated pins are TR5-F40W User www.terasic.com...

  • Page 17: Temperature Sensor And Fan Control

    Table 2-8 Temperature Sensor Pin Assignments, Schematic Signal Names, and Functions Schematic Stratix V GX Pin Description I/O Standard Signal Name Number Positive pin of temperature diode in TEMPDIODEp 2.5-V PIN_R6 Stratix V TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 18: Clock Circuit

    A clock buffer is used to duplicate the 50 MHz oscillator, so each bank of FPGA I/O bank 3/4/7/8 has two clock inputs. The two programming oscillators are low-jitter oscillators which are used to provide special and high quality clock signals for high-speed transceivers. Figure 2-10 shows the TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 19 I/O Standard Application Signal Name Frequency Pin Number OSC_50_B3B 2.5-V PIN_AV29 OSC_50_B3D 2.5-V PIN_AK23 OSC_50_B4A 2.5-V PIN_AL7 OSC_50_B4D 2.5-V PIN_AF17 50.0 MHz OSC_50_B7A 2.5-V PIN_G7 OSC_50_B7D 2.5-V PIN_P16 OSC_50_B8A 1.5-V/1.8-V/2.5-V PIN_E34 OSC_50_B8D 1.5-V/1.8-V/2.5-V PIN_J23 TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 20: Rs422 Serial Port

    Figure 2-11 shows the RS422 block diagram of the development board. The full-duplex LTC2855 is used to translate the RS422 signal, and the RJ45 is used as an external connector for the RS422 signal. TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 21: Flash Memory

    FPGA configuration data, user application data, and user code space. Each interface has a 16-bit data bus and the two devices combined allow for FPP x32 configuration. This device is part of the shared flash, SSRAM and MAX (FSM) bus, which connects to the flash TR5-F40W User www.terasic.com...
  • Page 22 Address bus 2.5-V PIN_AP24 FSM_A8 Address bus 2.5-V PIN_AM25 FSM_A9 Address bus 2.5-V PIN_AM26 FSM_A10 Address bus 2.5-V PIN_AP25 FSM_A11 Address bus 2.5-V PIN_AP22 FSM_A12 Address bus 2.5-V PIN_AL24 FSM_A13 Address bus 2.5-V PIN_AM23 TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 23 Data bus 2.5-V PIN_AC25 FSM_D24 Data bus 2.5-V PIN_AE25 FSM_D25 Data bus 2.5-V PIN_AD26 FSM_D26 Data bus 2.5-V PIN_AE26 FSM_D27 Data bus 2.5-V PIN_AE24 FSM_D28 Data bus 2.5-V PIN_AF25 FSM_D29 Data bus 2.5-V PIN_AF26 TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 24: Ssram

    2.5-V PIN_AR28 The IS61LPS51236A Synchronous Static Random Access Memory (SSRAM) device featured on the TR5-F40W development board is part of the shared FMS Bus, which connects to flash memory, SSRAM, and the MAX II CPLD (EEPM2210) System Controller. Table 2-13 lists the SSRAM pin assignments, signal names relative to the Stratix V GX device, in respectively.
  • Page 25 Data bus 2.5-V PIN_AD26 FSM_D26 Data bus 2.5-V PIN_AE26 FSM_D27 Data bus 2.5-V PIN_AE24 FSM_D28 Data bus 2.5-V PIN_AF25 FSM_D29 Data bus 2.5-V PIN_AF26 FSM_D30 Data bus 2.5-V PIN_AA27 FSM_D31 Data bus 2.5-V PIN_AB27 TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 26: Spf+ Ports

    Stratix V GX FPGA device and transform them to optical signals. The board includes cage assemblies for the SFP+ connectors. Figure 2-13 shows the connections between the SFP+ and Stratix V GX FPGA. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 27 Table 2-15 SFP+ B Pin Assignments, Schematic Signal Names, and Functions Schematic Stratix V GX Description I/O Standard Signal Name Pin Number SFPB_TX_p Transmitter data 1.4-V PCML PIN_AE4 SFPB_TX_n Transmitter data 1.4-V PCML PIN_AE3 TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 28 Signal loss indicator 2.5V PIN_AV11 SFPD_MOD0_PRSNT_n Module present 2.5V PIN_AU10 SFPD_MOD1_SCL Serial 2-wire clock 2.5V PIN_AU9 SFPD_MOD2_SDA Serial 2-wire data 2.5V PIN_AT9 SFPD_RATESEL0 Rate select 0 2.5V PIN_AU11 SFPD_RATESEL1 Rate select 1 2.5V PIN_AW11 TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 29: Pci Express

    PCI Express to allow different configurations to enable a x1, x4, or x8 PCIe. Table 2-18 summarizes the PCI Express pin assignments of the signal names relative to the Stratix V GX FPGA. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 30 PIN_AT38 PCIE_RX_n1 Add-in card receive bus 1.4-V PCML PIN_AT39 PCIE_RX_p2 Add-in card receive bus 1.4-V PCML PIN_AP38 PCIE_RX_n2 Add-in card receive bus 1.4-V PCML PIN_AP39 PCIE_RX_p3 Add-in card receive bus 1.4-V PCML PIN_AM38 TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 31: Sata

    The two Serial ATA (SATA) ports include one port for device and one port for host capable of implementing SATA solution with a design that consists of both host and target (device side) functions. Figure 2-15 depicts the host and device design examples. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 32 SATA host/device ports, a connection can be established between the two ports by using a SATA cable as Figure 2-16 depicts the associated signals connected. Table 2-19 lists the SATA pin assignments, signal names and functions. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 33 Differential transmit data output SATA_HOST_TX_n0 1.4-V PCML PIN_K1 before DC blocking capacitor Differential receive data input SATA_HOST_RX_n0 1.4-V PCML PIN_J4 after DC blocking capacitor Differential receive data input SATA_HOST_RX_p0 1.4-V PCML PIN_J3 after DC blocking capacitor TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 34: Hsmc: High -Speed Mezzanine Card

    There are three banks in this connector as Figure 2-17 shows the bank arrangement of signals with respect to the SAMTEC connector. Table 2-21 lists the mapping of the FPGA pin assignments to the HSMC connectors. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 35 The status of LED D25 will change to indicate the I/O standard of the HSMC port, as shown in Table 2-21. For example, LED D25 will turn red when the I/O Standard of HSMC is set to 2.5V. TR5-F40W User www.terasic.com...
  • Page 36 J3.5 – J3.6 2.5V (1) Users who connect a daughter card onto the HSMC ports need to pay close attention to the I/O standard between HSMC connector pins and daughter card system. For example, if the TR5-F40W User www.terasic.com Manual...
  • Page 37 Figure 2-19. Figure 2-19 JTAG Chain Default for a TR5-F40W board If a HSMC-based daughter card connected to the HSMC connector uses the JTAG interface, the position 3 of DIP switch (SW6) should be set to ‘Off’. In this case, from...
  • Page 38 Table 2–22 HSMC Pin Assignments, Schematic Signal Names, and Functions HSMC Schematic Signal Stratix V GX Description I/O Standard Pin # Name Pin Number HSMC_GXB_TX_p7 Transceiver TX bit 7 1.4-V PCML PIN_R36 HSMC_GXB_RX_p7 Transceiver RX bit 7 1.4-V PCML PIN_T38 TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 39 PIN_K22 HSMC_D2 LVDS TX or CMOS I/O LVDS or VCCIO PIN_N21 HSMC_D3 LVDS RX or CMOS I/O LVDS or VCCIO PIN_J22 HSMC_TX_p0 LVDS TX bit 0 or CMOS I/O LVDS or VCCIO PIN_M20 TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 40 LVDS RX bit 8n or CMOS I/O LVDS or VCCIO PIN_A22 HSMC_TX_p9 LVDS TX bit 9 or CMOS I/O LVDS or VCCIO PIN_A34 HSMC_RX_p9 LVDS RX bit 9 or CMOS I/O LVDS or VCCIO PIN_M26 TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 41 LVDS RX or CMOS I/O or HSMC_CLKIN_n2 LVDS or VCCIO PIN_P32 differential clock input Note for Table 2–22 *The signals E_HSMC_SDA and E_HSMC_SCL are level-shifted from 3.3V (HSMC) to VCCIO_HSMC (FPGA). TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 42: Chapter 3 System Builder

    The common mistakes that users encounter are the following:  Board damaged for wrong pin/bank voltage assignment.  Board malfunction caused by wrong device connections or missing pin counts for connected ends.  Performance dropped because of improper pin assignments TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 43: General Design Flow

    The Quartus II setting file contains information such as FPGA device type, top-level pin assignment, and I/O standard for each user-defined I/O pin. Finally, Quartus II programmer must be used to download SOF file to the FPGA board using JTAG interface. TR5-F40W User www.terasic.com Manual...

  • Page 44: Using System Builder

    The System Builder is located in the directory: "Tools\SystemBuilder" in the System CD. Users can copy the whole folder to a host computer without installing the utility. Before using the System Builder, execute the SystemBuilder.exe on the host computer as appears in Figure 3-2. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 45 Select the target board type and input project name as show in Figure 3-3.  Project Name: Specify the project name as it is automatically assigned to the name of the top-level design entity. Figure 3-3 Quartus II Project Name TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 46 Figure 3-5. SPF+ or SATA should be checked before users can start to specify the desired frequency in the programmable oscillators. As the Quartus project is created, System Builder automatically generates the associated controller TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 47 The System Builder also provides functions to restore default setting, loading a setting, and saving users’ board configuration file shown in Figure 3-6. Users can save the current board configuration information into a .cfg file and load it to the System Builder. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 48 Quartus II Project File <Project name>.qsf Quartus II Setting File <Project name>.sdc Synopsis Design Constraints file for Quartus II <Project name>.htm Pin Assignment Document (*) The Si570 Controller includes seven files: Si570_controller.v, initial_config.v, clock_divider.v, TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 49 For Si570, the Controller will be instantiated in the Quartus II top-level file as listed below: For CDM61004 configure, the System Builder will generate the CDCM6100x_Config and instantiates it in the Quartus II top-level file as listed below: TR5-F40W User www.terasic.com...
  • Page 50 If dynamic configuration for the oscillator is required, users need to modify the code according to users’ desired behavior. TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 51: Chapter 4 Flash Programming

    0x04940000. The NIOS II EDS tool nios-2-flash-programmer is used for programming the flash. Before programming, users need to translate their Quartus .sof and NIOS II .elf files into the .flash which is used by the TR5-F40W User www.terasic.com...

  • Page 52: Fpga Configure Operation

    Top batch file to download S5_PFL.sof and launch batch flash_program_bashrc_ub2 flash_program_bashrc_ub2 Translate .sof and .elf into .flash and programming flash with the generated .flash file Golden_top.sof Hardware design file for Hello Demo HELLO_NIOS.elf Software design file for Hello Demo TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 53 0x00, as shown in Figure 4-3. 2. In NIOS II processor options, select FLASH as reset vector memory and specify 0x04940000 as reset vector, as shown in Figure 4-4. TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 54: Restore Factory Settings

    This section describes how to restore the original factory contents to the flash memory device on the FPGA development board. Perform the following instructions: 1. Make sure the Nios II EDS and USB-Blaster II driver are installed. 2. Make sure the FPGA board and PC are connected with an UBS Cable. TR5-F40W User www.terasic.com Manual...
  • Page 55 The NIOS II EDS tool nios-2-flash-programmer programs the Flash based on the Parallel Flasher Loader design in the FPGA. The Parallel Flash Loader design is included in the default code PFL and the source code is available in the folder Demonstrations/ PFL in System CD. TR5-F40W User www.terasic.com...

  • Page 56: Chapter 5 Programmable Oscillator

    644.53125MHz or 322.265625MHz from the Si570. Figure 5-1 shows the block diagram of Si570 device. Users can modify the value of the three registers RFREQ, HS_DIV, and N1 to generate the desired output frequency. TR5-F40W User www.terasic.com Manual...
  • Page 57 8. Unfreeze the DCO and assert the NewFreq bit (bit 6 of Register 135). The I2C address of Si570 is zero and it supports fast mode operation whose transfer rate is up to 400 kbps. Table 5-1 shows the register table for Si570. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 58 Table 5-2 Si570 Register Table Output HS_DIV HS_DIV REF_CLK Frequency Register Register Register (MHz) Setting Setting Setting 0000101 02F40135A9(hex) 0000011 0302013B65(hex) 156.25 0000011 0313814290(hex) 0000001 0302013B65(hex) 312.5 0000001 0313814290(hex) 322.265625 0000011 02D1E127AF(hex) 644.53125 0000001 02D1E127AF(hex) TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 59 12 GigE PCI Express GigE 312.5 XGMII 10 GigE The both values of PRESCALER DIVIDER and FEEDBACK DIVIDER can be specified by the PR0 and PR1 control pins according to the following table: TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 60: Xample (Rtl)

    Recalibration process. In the FPGA board, the required output type is LVDS, so always set OS0 and SO1 to 0 and 1, respectively. In this section we will demonstrate how to use the Terasic Si570 Controller implemented in Verilog to control the Si570 programmable oscillator on the FPGA board. This controller IP can configure the Si570 to output a clock with a specific frequency via I2C interface.
  • Page 61 I2C interface clock of i2c_bus_controller. Finally, the initial_config block will generate a control signal to drive i2c_reg_controller which allows the Si570 controller to configure Si570 based on default settings. Figure 5-3 Block Diagram of Si570 Controller IP TR5-F40W User www.terasic.com Manual...
  • Page 62 “iStart” port to enable the Si570 Controller as shown in Figure 5-4. During Si570 configuring, the logic level of “oController_Ready” is low; when it rises to high again that TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 63 2. Locate the Verilog code shown below: always @(*) begin case(iFREQ_MODE) 3'h0 : //100Mhz begin new_hs_div = 4'b0101 ; new_n1 = 8'b0000_1010 ; fdco = 28'h004_E200 ; 3'h1 : //125Mhz begin new_hs_div = 4'b0101 ; new_n1 = 8'b0000_1000 ; TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 64 = 8'b0000_0100 ; fdco = 28'h005_0910 ; 3'h6 : //644.53125Mhz begin new_hs_div = 4'b0100 ; new_n1 = 8'b0000_0010 ; fdco = 28'h005_0910 ; default : //100Mhz begin new_hs_div = 4'b0101 ; new_n1 = 8'b0000_1010 ; TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 65 Users can refer to the Programmable Oscillator tool (See Figure 5-5) mentioned in below link to calculate the values of new_hs_div and new_n1, then, the fdco value can be calcuted with above ftdo equation. http://www.silabs.com/products/clocksoscillators/oscillators/Pages/oscillator-software-development -tools.aspx TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 66 .iCLK(iCLK), // system clock 50mhz .iRST_n(iRST_n), // system reset .oINITIAL_START(initial_start), .iINITIAL_ENABLE(1'b1), Changing the setting from ".iINITIAL_ENABLE(1'b1) " to ".iINITIAL_ENABLE(1'b0)" will disable the initialization function of Si570 Controller.  Design Tools  Quartus II 14.0 TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 67 3'b110 644.53125 3'b111  Power on the FPGA board.  Execute the demo batch file “Si570_Demonstration.bat” under the batch file folder, Si570_Demonstration\demo_batch  Press BUTTON1 can reconfigure the Si570.  Observe LED3 status. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 68 The program provides a menu in nios-terminal, as shown in Figure 5-7 to provide an interactive interface. With the menu, users can perform the test for the temperatures sensor and external PLL. Note. Inputting choice number should be followed by pressing ‘Enter’. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 69 In the external PLL programming test, the program will program the PLL first, and subsequently will use TERASIC QSYS custom CLOCK_COUNTER IP to count the clock count in a specified period to check whether the output frequency is changed as configured. To avoid a Quartus II compilation error, dummy transceiver controllers are created to receive the clock from the external PLL.
  • Page 70 , as shown in Figure 5-9.  For programming PLL Si570 test, please input key ‘2’ and press ‘Enter’ in the nios-terminal first, then select the desired output frequency , as shown in Figure 5-10. TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 71 Figure 5-8 Temperature Demo Figure 5-9 CDCM 61004 Demo TR5-F40W User www.terasic.com Manual June 20, 2018...
  • Page 72 Figure 5-10 Si570 Demo TR5-F40W User www.terasic.com Manual June 20, 2018...

  • Page 73: Additional Information

    Additional Information Here are the addresses where you can get help if you encounter problems:  Terasic Technologies 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, HsinChu City, 30070. Taiwan, 30070 Email: support@terasic.com Web: www.terasic.com TR5-F40W Web: TR5-F40W.terasic.com Date Version Changes 2012.7...

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