Dma Channel - Atmel AT91 Series Application Note

DMA Channel

The DMA Channel implementation copies the number of packets (4 words) defined by the user at each FIQ interrupt until
the remaining number of bytes is less than 1 packet (4 words). These remaining bytes are transferred at the following FIQ
interrupt, and the DMA is stopped by disabling the FIQ.
One inconvenience of this implementation is that non-banked registers are used. Therefore, it is mandatory to save these
registers before the transfer, and to restore them afterwards.
The main advantage is that the size of the transfer is controlled, and there is no risk of overwriting the memory.
The block is copied from the source to the destination by boundaries of packets. When no more whole packets can be
transferred, the remaining bytes (less than 16) are transferred in a way which optimizes the number of fetches:
• 2 words (8 to 15 remaining bytes)
• 1 word (4 to 7 remaining bytes)
• 1 half-word (2 or 3 remaining bytes)
• 1 byte (1 byte remaining)
The user can choose to increase, after each FIQ copy, the source pointer, the destination pointer, both pointers or neither.
Table 4. Registers Used
Register Parameter
r14 Link register - return address
r13 Temporary buffer address
r12 Increment mask
r11 Number of packets to copy per FIQ
r10 Block size (byte number)
r9 Destination address
r8 Source address
r6 to r7 Working registers (must be saved and restored)
r0 to r3 Transfer registers (must be saved and restored)
AT91 Series
4